ICS ELECTRONICS 4809A, Инструкция по эксплуатации

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The 4899A includes the expanded IEEE-488.2 status reporting structure
shown in Figure 3-1. The expanded status reporting structure conforms to
the SCPI 1994.0 Specification and builds on the IEEE 488.2 Standard status
structure with the addition of the Questionable, Operation and Modbus Error
registers. The Event and Status registers are controlled and queried with
the IEEE-488.2 common commands. The Status Byte Register may also
be read by serial polling the 4899A. The added Questionable and Operation
registers are controlled and queried with SCPI commands. The Modbus
Error register is read and cleared with the Modbus E? command.
As shown in Figure 3-1, IEEE 488.2 SRQ generation is a multilevel function
and is determined by the occurrence of an event that has its corresponding
enable bit set to ‘1’. The register outputs are summarized in the Status Byte
Register which generates the Service Request and pulls the SRQ line low.
SRQs are used to signal the bus controller that an event has occurred and/or
that the 4899A needs service. There are four major sources of SRQs, each
of which is summarized in a bit in the Status Byte Register. Three of the
sources are event registers with their own enabling bits and the fourth is
the Output Queue. The Event registers and the Output Queue are cleared
when read or by the *CLS command.
3.4.1 Event Registers
An event register captures 0 to 1 transitions in its associated condition
register or in the standard event register. An event bit becomes TRUE (1)
when the associated condition bit makes logical 0 to 1 transition. Once an
event bit is set it is held until the event register is read or cleared with the
*CLS command.
Each event register contains eight or sixteen bits. When the register is read,
its response is a decimal number that is the sum of the binary bit weights
of the bits that are logical 1s.
e.g., 23 decimal = 0001 0111 or 0000 0000 0001 0111 binary
Each event register bit has a corresponding enable bit. The enabling bits
are ANDed with the state of the event bits to create the summary condition
in the Status Byte Register. Unwanted conditions can be blocked from
generating SRQs by setting their corresponding enabling bit to a ‘0’. The