Hitachi HD64411 Q2, Руководство пользователя

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(5) DMA Write Cycle
Table 7-8 DMA Write Cycle
I t e m Symbol Min M a x U n i t
T e s t
Conditions N o t e s
RD
“High” Level Setup Time t
RDS
1/2
×
t
cyc0
– 9
— ns Figure 7-8
Figure 7-9 Multiplica-
tion off
RD
“High” Level Width t
RDHW
t
cyc0
— ns
RD
“High” Level Hold Time t
RDH
12 – 1/2
×
t
cyc0
— ns Multiplica-
tion off
RD
“Low” Level Width t
RDLW
3t
cyc0
— ns
Write Data Hold Time t
WRDH
0 — ns
Write Data Turn Off Time t
WRDOF
— 30 ns
Write Data Setup Time For
RD
t
WRDRS
2t
cyc0
— ns
DREQ
Delay Time t
DAD
— 25 ns
DREQ
Negate Time t
DAN
— 3t
cyc0
ns
DACK
Setup Time t
DAS
0 — ns 1
DACK
Hold Time t
DAH
0 — ns 2
Notes: 1. If the fall of
DACK
is later than the fall of
RD
, the specification of t
RDLW
is from the fall of
DACK
.
2. If the rise of
DACK
is earlier than the rise of
RD
, the specifications of t
RDLW
, t
WRDH
,
t
WRDOF
, and t
WRDRS
are from the rise of
DACK
.
(6) Interrupt Output
Table 7-9 Interrupt Output
I t e m Symbol Min M a x U n i t
T e s t
Conditions N o t e s
IRL
Delay Time t
IRD
— 25 ns Figure 7-10
IRL
“Low” Level Width t
IRLW
2t
cyc0
— ns