Hitachi HD64411 Q2, Руководство пользователя

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Table 7-4 Input Clocks (2) (Pins MODE2 to MODE0 = 000, 001, 010:
Multiplication On)
I t e m Symbol Min M a x U n i t
T e s t
Conditions N o t e s
Clock 0 Cycle Time t
cyc
30.3 50 ns Figure 7-4
×
1
Clock 0 Cycle Time t
cyc
60.6 100 ns
×
2
Clock 0 Cycle Time t
cyc
121.2 200 ns
×
4
Clock 0 “High” Level
Pulse Width t
CPWH
10.1 — ns
Clock 0 “Low” Level
Pulse Width t
CPWL
10.1 — ns
Clock Delay Time 1 t
CLKD1
— 10 ns
Clock Delay Time 2 t
CLKD2
— t
cyc
/4 + 11.7 ns
Clock Delay Time 3 t
CLKD3
— t
cyc
/2 + 11.7 ns
Clock Delay Time 4 t
CLKD4
— 3t
cyc
/4 + 11.7 ns
Clock i Cycle Time t
cyc0
30.3 50 ns
Clock i “High” Level
Pulse Width t
CiPWH
10.1 — ns
Clock i “Low” Level
Pulse Width t
CiPWL
10.1 — ns
Clock 1 Cycle Time t
cyc1
60.6 150 ns XW
≥
512
170 XW < 512
Clock 1 “High” Level
Pulse Width t
C1PWH
25.3 — ns
Clock 1 “Low” Level
Pulse Width t
C1PWL
25.3 — ns
Clock 1 Duty t
C1DT
0.5t
cyc1
– 1.7 0.5t
cyc1
+ 1.7 ns
Clock Rise Time t
cr
— 5 ns
Clock Fall Time t
cf
— 5 ns