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5 . 2
Register Updating
External Updating: Writing to an address-mapped registers from the CPU is called external
updating.
If external updating is performed in the interval from the raster following the end of screen display
until immediately before the rise of
VSYNC
, a register can be rewritten without causing display
flicker.
As the VBK flag and FRM flag in the status register (SR) are set to 1 at the start of vertical
blanking, external updating can be carried out using these flags.
Figures 5-1 (a) and (b) show the external update interval.
HSYNC
Display area
External update interval
VSYNC
VBK and FRM flags
both set to 1
Figure 5-1 (a) External Update Interval (Interlace Mode)
Содержание HD64411 Q2
Страница 17: ...10 ...
Страница 31: ...24 ...
Страница 108: ...101 Example 0 0 Work coordinates Rendering coordinates XC YC ...
Страница 110: ...103 Example Old XC YC Old XC XC old YC YC 0 0 Work coordinates Rendering coordinates XC YC ...
Страница 112: ...105 Example 0 0 Work coordinates Rendering coordinates XO1 YO1 XO1 DX2 YO1 DY2 XO1 DX1 YO1 DY1 LINE ...
Страница 116: ...109 Example 0 0 Work coordinates Rendering coordinates XMIN YMIN XMAX YMAX ...
Страница 118: ...111 Example 0 0 Work coordinates Rendering coordinates XMAX YMAX ...
Страница 120: ...113 Example 0 0 Work coordinates XMIN YMIN XMAX YMAX ...
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Страница 213: ...206 Figure 7 20 TV Sync Mode Display Timing When DOT 0 or DOT 1 and EXHSYNC cycle is even multiple of CLK1 cycle ...