Hitachi HD64411 Q2, Руководство пользователя

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2
CPG0 CPG1
Rendering unit
Rendering
buffer unit
CPU-I/F
∆
YUV>>RGB
Display unit
RGB >> YCrCb
Display buffer
unit
Color palette
UGM
I/F
Chip
manager
DMA control
CLKi
Quick 2D graphics renderer
Frame buffer 1
Binary/multi-valued
source
Frame buffer 0
Binary work area
Display list
UGM (unified graphics memory)
CLK0
CLK0
DCLK
SYNC
NTSC
MIX
Digital video
encoder
R: 6
G: 6
B: 6
16 bits
(YCrCb: 8, 8/8 bits)
EDO-DRAM: 4 M to 32 M
D/A
D/A
D/A
Address (16)
Address
control
(22)
Data
(16)
Data (16)
SuperH
External video
Figure 1-1 Overview of Q2 System
1 . 2 Block Diagram
Figure 1-2 shows a block diagram of the Q2. The functions of the various blocks in figure 1-2 are
as follows.
•
Rendering unit
Performs fetching and interpretation of the display list on the UGM, references the source data
on the UGM, and output drawing data to the drawing-side frame buffer on the UGM.
•
Rendering buffer unit
Buffers data and addresses between the rendering unit and the UGM, and outputs them
efficiently.
•
CPU interface unit
Performs control relating to connection to the CPU bus.
•
Memory interface unit
Performs control relating to connection to the UGM bus.
•
Display unit
Controls the control signals sent to the CRT device.