Commissioning
59/90
7.6.4
Application case 4
Like application case 2, but with analysis of input signals
This application case corresponds to application case 2, but in addition to
Ethernet communication, one to four input signals are included in the
analysis. When there is an edge reverse at the digital input, a pseudo
Ethernet frame with time stamp is generated in the NANL-B500G-RE
analyzer device.
The analyzer device NANL-B500G-RE can analyze the following processes
and parameters:
·
the communication between two devices for two channels,
·
the forwarding time through the device,
·
the cycle time and the jitter in the cyclically running protocols,
·
the changes of the data in the Ethernet frame through the device,
·
protocol-stack processing time from Ethernet frame reception to digital
output switching,
·
the input signal events on the basis of time-stamps,
·
the number of erroneous Ethernet frames.
Device Destruction
·
Only apply a signal voltage of 3.3 V or 24 V to the I/O signal pins of the
external I/O interface
! Higher signaling voltages lead to severe
damage to the NANL-B500G-RE device!
·
To operate the NANL-B500G-RE device, take a maximum of 1 mA (at
3.3V) or 600 mA (at 24V) current at the I/O signal pins on the
external I/
O interface
. Otherwise the netX chip and other components may be
damaged.
Damage of externally attached Hardware
NANL-B500G-RE
·
If the +3.3V output of the external IO interface is enabled (I/O status
LED lights up orange), externally attached hardware could be damaged
as voltage is driven.
·
If the +24V output of the external IO interface is enabled (I/O status LED
lights up red), externally attached hardware could be damaged as
voltage is driven.
netANALYZER device NANL-B500G-RE | Installation, operation and hardware description
DOC091110UM26EN | Revision 26 | English | 2019-07 | Released | Public
© Hilscher 2007-2019