23
UCP
-
3901
User Manual
IQUCP25 / IQUCP50 Block Diagram
These are the features supported in the initial release and do not necessarily represent all
hardware connectors available.
IQUCP 25 with Essence Processing SDC
Figure 1 - 5:
IQUCP25-EP Universal Compute Processor Functional Block Diagram
IQUCP 50 with Essence Processing SDC
Figure 1 - 6:
IQUCP5000-EP Universal Compute Processor Functional Block Diagram
Network Intelligence, Control & Monitoring
IQUCP25-EP Essence Processing Block Diagram
PTP, Bi & Tri-Level
Reference
Rx
Tx
SFP 1
25GbE
Rx
Tx
SFP 2
25GbE
Rx
Tx
SFP 1
25GbE
Rx
Tx
SFP 2
25GbE
NMOS IS-04/IS-05
ST 2059
ST 2110-30
ST 2110-30
ST 2110-30
ST 2110-30
16x16
Audio
Shuffler
ST 2110-40
ST 2110-20
ANC
Insert
Audio
Embed
2:1
ST 2022-6
IP
Decap
With
-7
Dual
Rx
Hitless
IQH3B/IQH4B Frame
Ref Inputs
12G/3G/HD/SD 1-4
3G/HD/SD 5-16
ST 2110-40
ST 2110-20
ST 2022-6
Audio
De-embed
ANC
Extract
16x16
Audio
Shuffler
Top
of
frame
Align-
ment
ST 2110-30
ST 2110-30
ST 2110-30
ST 2110-30
IQH3B/IQH4B Frame
Controller
IP
Encap
With
-7
Dual
TX
12G/3G/HD/SD 1-4
3G/HD/SD 5-16
Depending on the FPGA configuration
loaded, there may be two
blocks of 12G to IP and two blocks
of IP to 12G; or there may be as
many blocks needed for your HD/3G
configurations. These will include
quad-stream to single 12G SDI or
2SI quad-link to single stream UHD.
Single stream UHD only supported
in SMPTE ST 2110.
0 to 16 SDI to IP Channels
0 to 16 IP to SDI Channels
Network Intelligence, Control & Monitoring
IQUCP5000-EP Essence Processing Block Diagram
PTP, Bi & Tri-Level
Reference
Rx
Tx
QSFP 1
50GbE
Rx
Tx
QSFP 2
50GbE
Rx
Tx
QSFP 1
50GbE
Rx
Tx
QSFP 2
50GbE
NMOS IS-04/IS-05
ST 2059
ST 2110-30
ST 2110-30
ST 2110-30
ST 2110-30
16x16
Audio
Shuffler
ST 2110-40
ST 2110-20
ANC
Insert
Audio
Embed
2:1
ST 2022-6
IP
Decap
With
-7
Dual
Rx
Hitless
IQH3B/IQH4B Frame
Ref Inputs
12G/3G/HD/SD 1-4
3G/HD/SD 5-16
ST 2110-40
ST 2110-20
ST 2022-6
Audio
De-embed
ANC
Extract
16x16
Audio
Shuffler
Top
of
frame
Align-
ment
ST 2110-30
ST 2110-30
ST 2110-30
ST 2110-30
IQH3B/IQH4B Frame
Controller
IP
Encap
With
-7
Dual
TX
12G/3G/HD/SD 1-4
3G/HD/SD 5-16
Depending on the FPGA configuration
loaded, there may be four
blocks of 12G to IP or four blocks
of IP to 12G; or there may be as
many blocks needed for your HD/3G
configurations. These will include
quad-stream to single 12G SDI or
2SI quad-link to single stream UHD.
Single stream UHD only supported
in SMPTE ST 2110.
0 to 16 SDI to IP Channels
0 to 16 IP to SDI Channels
Содержание IQUCP25
Страница 8: ...8 Notices ...
Страница 47: ...47 UCP 3901 User Manual IQUCP2504 2B3 IQUCP2505 3B3 IQUCP5000 2B3 ...
Страница 48: ...48 IQUCP Card Installation and Operation Rear Panel and Connectors IQUCP5001 3B3 IQUCP5002 2B3 IQUCP5003 3B3 ...
Страница 52: ...52 IQUCP Card Installation and Operation Remote control using RollCall ...
Страница 58: ...58 Connections and Cabling About HDMI Type Signal Connections ...
Страница 70: ...70 Connecting to the Card s Configuration Interface Setting Values in RollCall ...
Страница 167: ...167 UCP 3901 User Manual Ethernet Arcnet Not currently used ...
Страница 246: ...246 MADI Processing SDC Ethernet Arcnet Ethernet Arcnet Not currently used ...
Страница 308: ...308 Multiviewer SDC Timer Request Protocol ...