706
PWM
Notes on Changing the PWM Setting
................................................ 531
PWM Control 0 Register
PWM Control 0 Register
................................... 524
PWM1 and PWM2 Compare Registers
PWM1 and PWM2 Compare Registers
PWM1 Select Registers
PWM1 Select Registers
.................................... 527
PWM2 Select Registers
PWM2 Select Registers
.................................... 529
R
RAM Area
RAM Area
......................................................... 28
Rate and Data Register
Rate and Data Register (URD)
........................... 320
Rate and Data Register (URD) Contents
RCR
Reception Complete Register (RCR)
RDR
Bit Configuration of Reception and Transmission Data
Registers
(RDR2/RDR3 and TDR2/TDR3)
Reception Data Register (RDR2/RDR3)
Receive and Transmit Error Counters
Receive and Transmit Error Counters
(RTEC)
.............................................. 476
Receive and Transmit Error Counters
(RTEC) Contents
................................. 476
Receive Operation
Flag Set Timings for a Receive Operation
......................................... 331
Flag Set Timings for a Receive Operation (in Mode0,
Mode1, Mode3)
.................................. 330
Status Flag during Transmit and Receive
Operation
........................................... 333
Receive Overrun
Receive Overrun
.............................................. 505
Receive Overrun Register
Receive Overrun Register (ROVRR)
Received Message
Storing Received Message
................................ 504
Reception
...................................... 506
Procedure for Reception by Message Buffer
(x)
...................................................... 512
Reception and Transmission Data Register
Bit Configuration of Reception and Transmission Data
Registers
(RDR2/RDR3 and TDR2/TDR3)
Reception Complete Register
Reception Complete Register (RCR)
Reception Data Register
Reception Data Register (RDR2/RDR3)
Reception Flowchart
Reception Flowchart of the CAN Controller
Reception Interrupt
Reception Interrupt Generation and Flag Set
............................................... 369
Reception Interrupt Enable Register
Reception Interrupt Enable Register (RIER)
Register
16-bit Reload Timer Register
............................ 226
8/10-bit A/D Converter Registers
8/16-bit PPG Registers
..................................... 254
I/O Port Registers
............................................ 171
I
2
C Interface Registers
..................................... 408
Output Compare Register
................................. 204
Serial I/O Registers
.......................................... 439
Sound Generator Registers
................................ 535
Stepping Motor Controller Registers
UART0, UART1 Registers
............................... 314
UART2, UART3 Registers
............................... 349
Register Bank
.................................................... 45
Register Bank Pointer
Register Bank Pointer (RP)
................................. 42
Reload Register
Reload Register (PRLL/PRLH)
Reload Value
Relationship between 8/16-bit PPG Reload Value and
Pulse Width
........................................ 263
Remote Frame
Processing for Reception of Data Frame and Remote
Frame
................................................ 505
Remote Frame Receiving Wait Register
Remote Frame Receiving Wait Register
(RFWTR)
........................................... 483
Remote Request Receiving Register
Remote Request Receiving Register
........................................... 488
Reset
Causes of a Reset
............................................. 126
Notes about Reset Cause Bits
............................ 134
............................ 131
Reset Cause Bits
.............................................. 133
Status of Pins during a Reset
............................. 136
Reset Cause Bits
Notes about Reset Cause Bits
............................ 134
Reset Cause Bits
.............................................. 133
Reset Causes
Reset Causes and Oscillation Stabilization Wait
................................................ 128
Restarting Erasing
Restarting Erasing of Flash Memory Sectors
Содержание MB90390 Series
Страница 2: ......
Страница 4: ......
Страница 17: ...xiii APPENDIX D List of Interrupt Vectors 690 INDEX 695 ...
Страница 18: ...xiv ...
Страница 132: ...104 CHAPTER 5 CLOCKS ...
Страница 152: ...124 CHAPTER 6 CLOCK MODULATOR ...
Страница 210: ...182 CHAPTER 11 TIME BASE TIMER ...
Страница 218: ...190 CHAPTER 12 WATCHDOG TIMER ...
Страница 264: ...236 CHAPTER 14 16 BIT RELOAD TIMER WITH EVENT COUNT FUNCTION ...
Страница 274: ...246 CHAPTER 15 WATCH TIMER ...
Страница 306: ...278 CHAPTER 17 DTP EXTERNAL INTERRUPTS ...
Страница 338: ...310 CHAPTER 18 8 10 BIT A D CONVERTER ...
Страница 364: ...336 CHAPTER 19 UART0 UART1 ...
Страница 398: ...370 CHAPTER 20 UART2 UART3 Figure 20 5 2 ORE Set Timing Receive data RDRF ORE ...
Страница 432: ...404 CHAPTER 20 UART2 UART3 ...
Страница 482: ...454 CHAPTER 22 SERIAL I O ...
Страница 560: ...532 CHAPTER 24 STEPPING MOTOR CONTROLLER ...
Страница 582: ...554 CHAPTER 27 ROM MIRRORING MODULE ...
Страница 632: ...604 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION ...
Страница 722: ...694 APPENDIX ...
Страница 723: ...695 INDEX The index follows on the next page This is listed in alphabetic order ...
Страница 740: ......