Fujitsu MB90390 Series, Руководство по оборудованию

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CHAPTER 7 RESETS
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Correspondence between Reset Cause Bits and Reset Causes
Figure 7.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC).
Table 7.5-1 maps the correspondence between the reset cause bits and reset causes. See Table 12.1-2 in
Section "12.1 Outline of Watchdog Timer", for details.
Figure 7.5-2 Configuration of Reset Cause Bits (Watchdog Timer Control Register)
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Notes about Reset Cause Bits
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Multiple reset causes generated at the same time
When multiple reset causes are generated at the same time, the corresponding reset cause bits of the
watchdog timer control register (WDTC) are also set to "1". If, for example, an external reset request via
the RST pin and the watchdog timer overflow occur at the same time, the ERST and the WRST bits are
both set to "1".
●
Power-on reset
For a power-on reset, because the PONR bit is set to "1" but all other reset cause bits are undefined, the
software should be programmed so that it will ignore all reset cause bits except the PONR bit if it is "1".
PONR - WRST ERST SRST WTE WT1 WT0
R R R R W W W
R : Read only
W : Write only
X : Undefined
Address: Initial value
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit8
(TBTC)
Watchdog timer control register (WDTC)
0000A8
H
X - X X X X X
B
-
Table 7.5-1 Correspondence between Reset Cause Bits and Reset Causes
Reset cause PONR WRST ERST SRST
Power-on reset 1 X X X
Watchdog timer overflow * 1 * *
External reset request via RST pin * * 1 *
Software reset request * * * 1
*: Previous state defined
X: Undefined