429
CHAPTER 21 400 kHz I
2
C INTERFACE
■
I
2
C Clock Control Register (ICCR) Contents
Table 21.2-8 Function of Each Bit of the I
2
C Clock Control Register
Bit name
Function
bit15
Undefined
This bit always returns "0" during reading.
bit14
NSF:
IO pad noise filter
enable bit
This bit enables the noise filters built into the SDA and SCL I/O pads.
It should be set to "1" if the interface is transmitting or receiving at data rates above 100
kbit.
MB90V390H:
The noise filter will suppress single spikes with a pulse width of 0 ns (minimum) and
between 1 and 1.5 cycles of internal-bus (maximum). The maximum depends on the
phase relationship between I
2
C signals (SDA, SCL) and machine clock.
MB90394HA, MB90V390HA, MB90V390HB:
The noise filter will suppress single spikes with a pulse width between 0 ns (minimum)
and a maximum value according to the setting of the SEL1, SEL0 bits in the INFCR
register. Refer to Table 21.2-11. The maximum depends on the phase relationship
between I
2
C signals (SDA, SCL) and machine clock.
bit13
EN:
Enable bit
This bit enables the I
2
C interface operation. It can only be set by the user but may be
cleared by the user and the hardware.
"0": Interface disabled
"1": Interface enabled
When this bit is set to "0" all bits in the IBSR register and IBCR register (except the
BER and BEIE bits) are cleared and the module is disabled and the I
2
C lines are left
open. It is cleared by the hardware if a bus error occurs (BER = 1 in IBCR).
Notes:
•
When the operation of the I
2
C interface is prohibited, sending and receiving is
stopped at once.
•
Please prohibit operating after confirming the generation of the stop condition
(BB=0 of IBSR) when you prohibit the operation of the I
2
C interface after written
"0" to the MSS bit and the stop condition is generated (EN=0 of ICCR).
bit12 to
bit8
CS4 to CS0:
Clock prescaler
bits
These bits select the serial bit rate. They can only be changed if the interface is disabled
(EN = 0) or the EN bit is being cleared in the same write access.
n
CS4
CS3
CS2
CS1
CS0
1
0
0
0
0
1
Bit rate:
φ
/ 28(+1)
Bit rate:
φ
/ 40(+1)
Bit rate:
φ
/ 52(+1)
Bit rate:
φ
/ 64(+1)
Bit rate:
φ
/ 400(+1)
2
0
0
0
1
0
3
0
0
0
1
1
4
0
0
1
0
0
...
31
1
1
1
1
1
(+1) means: Add 1 to divisor, if noise filter is enabled
Содержание MB90390 Series
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Страница 17: ...xiii APPENDIX D List of Interrupt Vectors 690 INDEX 695 ...
Страница 18: ...xiv ...
Страница 132: ...104 CHAPTER 5 CLOCKS ...
Страница 152: ...124 CHAPTER 6 CLOCK MODULATOR ...
Страница 210: ...182 CHAPTER 11 TIME BASE TIMER ...
Страница 218: ...190 CHAPTER 12 WATCHDOG TIMER ...
Страница 264: ...236 CHAPTER 14 16 BIT RELOAD TIMER WITH EVENT COUNT FUNCTION ...
Страница 274: ...246 CHAPTER 15 WATCH TIMER ...
Страница 306: ...278 CHAPTER 17 DTP EXTERNAL INTERRUPTS ...
Страница 338: ...310 CHAPTER 18 8 10 BIT A D CONVERTER ...
Страница 364: ...336 CHAPTER 19 UART0 UART1 ...
Страница 398: ...370 CHAPTER 20 UART2 UART3 Figure 20 5 2 ORE Set Timing Receive data RDRF ORE ...
Страница 432: ...404 CHAPTER 20 UART2 UART3 ...
Страница 482: ...454 CHAPTER 22 SERIAL I O ...
Страница 560: ...532 CHAPTER 24 STEPPING MOTOR CONTROLLER ...
Страница 582: ...554 CHAPTER 27 ROM MIRRORING MODULE ...
Страница 632: ...604 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION ...
Страница 722: ...694 APPENDIX ...
Страница 723: ...695 INDEX The index follows on the next page This is listed in alphabetic order ...
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