708
Watchdog Timer Behavior in Stop Mode, Time-base
Timer Mode, and Sleep Mode
SLP
Priorities of the STP,SLP,and TMD Bits
SMCS
Upper Byte of Serial Mode Control Status Register
(SMCS)
.............................................. 440
SMR
Serial Mode Register (SMR2/SMR3)
Software Interrupt
Software Interrupt Operation
............................... 69
Software Interrupts
....................................... 55, 69
Structure of Software Interrupts
........................... 69
Sound Generator
Block Diagram of Sound Generator
Sound Generator Registers
................................ 535
Sound Generator Control Register
Sound Generator Control Register (Lower)
Sound Generator Control Register (SGCR) (Upper)
Contents
............................................. 538
Sound Generator Control Register (Upper)
Special Registers
................................................ 36
SSP
User Stack Pointer (USP) and System Stack Pointer
(SSP)
................................................... 40
SSR
Serial Status Register (SSR2/SSR3)
Standby Mode
Notes on Accessing the Low-power Consumption
Mode Control Register (LPMCR) to Enter
the Standby Mode
............................... 161
Release of the Standby Mode
by an Interrupt
.................................... 159
Standby Mode
.................................................. 139
Switching to a Standby Mode and Interrupt
Notes on the Transition to Standby Mode
Operation Status during Standby Mode
Start Conditions
Start Conditions
............................................... 432
Startup Sequence
Recommended Startup Sequence for Frequency
................................ 121
Recommended Startup Sequence for Phase
................................ 121
State
State during Bus Operation Stop (HALT=1)
State Transition
State Transition Diagram of the
Watchdog Timer
................................. 187
Status Change Diagram
Status Change Diagram
..................................... 156
Status of Pins
Status of Pins after Mode Data is Read
Status of Pins during a Reset
............................. 136
Status Register
Status Register (USR)
...................................... 317
Stepping Motor Controller
Block Diagram of Stepping Motor
Controller
........................................... 522
Stepping Motor Controller Registers
Stop Conditions
Stop Conditions
............................................... 432
Stop Conversion Mode
Sample Program for Stop Conversion Mode Using
EI
2
................................................ 307
Stop Mode
Release of the Stop Mode
................................. 160
Switching to the Stop Mode
.............................. 153
Watchdog Timer Behavior in Stop Mode, Time-base
STP
Priorities of the STP,SLP,and TMD Bits
Structure
Structure
........................................................... 72
Structure of Instruction Map
............................. 660
Sub-second Register
Sub-second Register
......................................... 244
Suspending Erasing
Suspending Erasing of Flash Memory
............................................... 582
Synchronization Methods
Synchronization Methods
................................. 381
Synchronous Mode
Operation in Synchronous Mode
(Operation Mode 2)
............................. 385
System Stack Pointer
User Stack Pointer (USP) and System Stack Pointer
(SSP)
................................................... 40
T
TBTC
Time-base Timer Control Register (TBTC)
TCANR
Transmission Cancel Register (TCANR)
TCR
Transmission Complete Register (TCR)
TDR
Bit Configuration of Reception and Transmission Data
Registers
(RDR2/RDR3 and TDR2/TDR3)
Transmission Data Register (TDR2/TDR3)
Temporary Sector Protect
Temporary Sector Protect Cancellation
Ten Bit Address Mask Register
Ten Bit Address Mask Register (ITMK)
Содержание MB90390 Series
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Страница 4: ......
Страница 17: ...xiii APPENDIX D List of Interrupt Vectors 690 INDEX 695 ...
Страница 18: ...xiv ...
Страница 132: ...104 CHAPTER 5 CLOCKS ...
Страница 152: ...124 CHAPTER 6 CLOCK MODULATOR ...
Страница 210: ...182 CHAPTER 11 TIME BASE TIMER ...
Страница 218: ...190 CHAPTER 12 WATCHDOG TIMER ...
Страница 264: ...236 CHAPTER 14 16 BIT RELOAD TIMER WITH EVENT COUNT FUNCTION ...
Страница 274: ...246 CHAPTER 15 WATCH TIMER ...
Страница 306: ...278 CHAPTER 17 DTP EXTERNAL INTERRUPTS ...
Страница 338: ...310 CHAPTER 18 8 10 BIT A D CONVERTER ...
Страница 364: ...336 CHAPTER 19 UART0 UART1 ...
Страница 398: ...370 CHAPTER 20 UART2 UART3 Figure 20 5 2 ORE Set Timing Receive data RDRF ORE ...
Страница 432: ...404 CHAPTER 20 UART2 UART3 ...
Страница 482: ...454 CHAPTER 22 SERIAL I O ...
Страница 560: ...532 CHAPTER 24 STEPPING MOTOR CONTROLLER ...
Страница 582: ...554 CHAPTER 27 ROM MIRRORING MODULE ...
Страница 632: ...604 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION ...
Страница 722: ...694 APPENDIX ...
Страница 723: ...695 INDEX The index follows on the next page This is listed in alphabetic order ...
Страница 740: ......