Freescale Semiconductor MC9S12ZVM series, Справочное руководство

Страница: 784 / 825

Appendix H SPI Electrical Specifications
MC9S12ZVM Family Reference Manual Rev. 1.3
784 Freescale Semiconductor
Figure H-3. SPI Master Timing (CPHA=1)
Table H-1. SPI Master Mode Timing Characteristics (Junction Temperature From -40
°
C To +175
°
C)
Num C Characteristic Symbol Unit
Min Typ Max
1 D SCK Frequency f
sck
1/2048 — 1
/
2
(1)(2)
1. See Figure H-4.
2. f
bus
max is 40MHz at temperatures above 150
°
C
f
bus
1 D SCK Period t
sck
2 — 2048 t
bus
2 D Enable Lead Time t
lead
— 1/2 — t
sck
3 D Enable Lag Time t
lag
— 1/2 — t
sck
4 D Clock (SCK) High or Low Time t
wsck
— 1/2 — t
sck
5 D Data Setup Time (Inputs) t
su
4 — —
ns
6 D Data Hold Time (Inputs) t
hi
5 — —
ns
9 D Data Valid after SCK Edge t
vsck
— — 10
ns
10 D Data Valid after SS fall (CPHA=0) t
vss
— — 9
ns
11 D Data Hold Time (Outputs) t
ho
-1.2 — —
ns
12 D Rise and Fall Time Inputs t
rfi
— — 8
ns
13 D Rise and Fall Time Outputs t
rfo
— — 8
ns
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
1
5 6
MSB IN
2
BIT 6 . . . 1
LSB IN
MASTER MSB OUT
2
MASTER LSB OUT
BIT 6 . . . 1
4 4
9
12 13
11
(CPOL
=
0)
(CPOL
=
1)
SS
1
(OUTPUT)
2
12 13 3
1. If enabled.
2. LSBFE = 0. For LSBFE = 1, bit order is LSB, bit 1, ..., bit 6, MSB.