Freescale Semiconductor MC9S12ZVM series, Справочное руководство

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Chapter 14 Pulse Width Modulator with Fault Protection (PMF15B6CV3)
MC9S12ZVM Family Reference Manual Rev. 1.3
514 Freescale Semiconductor
of 4095 PWM clock cycles. Deadtime is affected by changes to the prescaler value. The deadtime duration
is determined as follows:
T
DEAD_A
= PMFDTMA / f
PWM_A
= PMFDTMA
×
P
A
×
T
core
Eqn. 14-1
14.3.2.24 PMF Enable Control B Register (PMFENCB)
Address: Module Base + 0x0028 Access: User read/write
(1)
1. Read: Anytime. Returns zero if MTG is clear.
Write: Anytime if MTG is set.GLDOKB and RSTRTB cannot be modified after the WP bit is set.
7 6 5 4 3 2 1 0
R
PWMENB GLDOKB
0 0 0
RSTRTB LDOKB PWMRIEB
W
Reset 0 0 0 0 0 0 0 0
Figure 14-29. PMF Enable Control B Register (PMFENCB)
Table 14-28. PMFENCB Field Descriptions
Field Description
7
PWMENB
PWM Generator B Enable — If MTG is clear, this bit reads zero and cannot be written.
If MTG is set, this bit when set enables the PWM generator B and the PWM2 and PWM3 outputs. When
PWMENB is clear, PWM generator B is disabled, and the PWM2 and PWM3 outputs are in their inactive states
unless the corresponding OUTCTL bits are set.
After setting this bit a reload event is generated at the beginning of the PWM cycle.
0 PWM generator B and PWM2–3 outputs disabled unless the respective OUTCTL bit is set
1 PWM generator B and PWM2–3 outputs enabled
6
GLDOKB
Global Load Okay B — When this bit is set, a PMF external global load OK defined on device level replaces the
function of LDOKB. This bit cannot be modified after the WP bit is set.
0 LDOKB controls double reload of buffered registers
1 PMF external global load OK controls reload of double buffered registers
2
RSTRTB
Restart Generator B — When this bit is set, PWM generator B will be restarted at the next commutation event.
This bit cannot be modified after the WP bit is set.
0 No PWM generator B restart at the next commutation event
1 PWM generator B restart at the next commutation event
1
LDOKB
Load Okay B — If MTG is clear, this bit reads zero and cannot be written.
If MTG is set, this bit loads the PRSCB bits, the PMFMODB register and the PMFVAL2-3 registers into a set of
buffers. The buffered prescaler divisor B, PWM counter modulus B value, PWM2–3 pulse widths take effect at
the next PWM reload.
Set LDOKB by reading it when it is logic zero and then writing a logic one to it. LDOKB is automatically cleared
after the new values are loaded, or can be manually cleared before a reload by writing a logic zero to it. Reset
clears LDOKB.
0 Do not load new modulus B, prescaler B, and PWM2–3 values
1 Load prescaler B, modulus B, and PWM2–3 values
Note: Do not set PWMENB bit before setting the LDOKB bit and do not clear the LDOKB bit at the same time as
setting the PWMENB bit.
0
PWMRIEB
PWM Reload Interrupt Enable B — If MTG is clear, this bit reads zero and cannot be written.
If MTG is set, this bit enables the PWMRFB flag to generate CPU interrupt requests.
0 PWMRFB CPU interrupt requests disabled
1 PWMRFB CPU interrupt requests enabled