Freescale Semiconductor MC9S12ZVM series, Справочное руководство

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Chapter 9 Analog-to-Digital Converter (ADC12B_LBA_V1)
MC9S12ZVM Family Reference Manual Rev. 1.3
318 Freescale Semiconductor
9.4.2 Register Descriptions
This section describes in address order all the ADC12B_LBA registers and their individual bits.
9.4.2.1 ADC Control Register 0 (ADCCTL_0)
Read: Anytime
Write:
• Bits ADC_EN, ADC_SR, FRZ_MOD and SWAI writable anytime
• Bits MOD_CFG, STR_SEQA and ACC_CFG[1:0] writable if bit ADC_EN clear or bit
SMOD_ACC set
Module Base + 0x0000
15 14 13 12 11 10 9 8
R
ADC_EN ADC_SR FRZ_MOD SWAI ACC_CFG[1:0] STR_SEQA MOD_CFG
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 9-4. ADC Control Register 0 (ADCCTL_0)
Table 9-2. ADCCTL_0 Field Descriptions
Field Description
15
ADC_EN
ADC Enable Bit — This bit enables the ADC (e.g. sample buffer amplifier etc.) and controls accessibility of ADC
register bits. When this bit gets cleared any ongoing conversion sequence will be aborted and pending results
or the result of current conversion gets discarded (not stored). The ADC cannot be re-enabled before any
pending action or action in process is finished or aborted, which could take up to a maximum latency time of
t
DISABLE
(see device reference manual for more details).
Because internal components of the ADC are turned on/off with this bit, the ADC requires a recovery time period
(t
REC
) after ADC is enabled until the first conversion can be launched via a trigger.
0 ADC disabled.
1 ADC enabled.
14
ADC_SR
ADC Soft-Reset — This bit causes an ADC Soft-Reset if set after a severe error occurred (see list of severe
errors in
Section 9.4.2.9, “ADC Error Interrupt Flag Register (ADCEIF) that causes the ADC to cease operation).
It clears all overrun flags and error flags and forces the ADC state machine to its idle state. It also clears the
Command Index Register, the Result Index Register, and the CSL_SEL and RVL_SEL bits (to be ready for a new
control sequence to load new command and start execution again from top of selected CSL).
A severe error occurs if an error flag is set which cause the ADC to cease operation.
In order to make the ADC operational again an ADC Soft-Reset must be issued.
Once this bit is set it can not be cleared by writing any value. It is cleared only by ADC hardware after the
Soft-Reset has been executed.
0 No ADC Soft-Reset issued.
1 Issue ADC Soft-Reset.
13
FRZ_MOD
Freeze Mode Configuration — This bit influences conversion flow during Freeze Mode.
0 ADC continues conversion in Freeze Mode.
1 ADC freezes the conversion at next conversion boundary at Freeze Mode entry.
12
SWAI
Wait Mode Configuration — This bit influences conversion flow during Wait Mode.
0 ADC continues conversion in Wait Mode.
1 ADC halts the conversion at next conversion boundary at Wait Mode entry.