Freescale Semiconductor MC9S12ZVM series, Справочное руководство

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Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6)
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor 295
8.4.2 Startup from Reset
An example for startup of the clock system from Reset is given in Figure 8-36 .
Figure 8-36. Startup of clock system after Reset
8.4.3 Stop Mode using PLLCLK as source of the Bus Clock
An example of what happens going into Stop Mode and exiting Stop Mode after an interrupt is shown in
Figure 8-37 . Disable PLL Lock interrupt (LOCKIE=0) before going into Stop Mode.
Figure 8-37. Stop Mode using PLLCLK as source of the Bus Clock
Depending on the COP configuration there might be an additional significant latency time until COP is
active again after exit from Stop Mode due to clock domain crossing synchronization. This latency time
occurs if COP clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for
details).
System
PLLCLK
Reset
f
VCORST
CPU
reset state
vector fetch, program execution
LOCK
POSTDIV $03 (default target f
PLL
=f
VCO
/4 = 12.5MHz)
f
PLL
increasing
f
PLL
=12.5MHz
t
lock
SYNDIV
$18 (default target f
VCO
=50MHz)
$01
f
PLL
=25 MHz
example change
of POSTDIV
768 cycles
) (
PLLCLK
CPU
LOCK
t
lock
STOP instruction execution interrupt continue execution
wake up
t
STP_REC