Freescale Semiconductor MC9S12ZVM series, Справочное руководство

Страница: 256 / 825

Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6)
MC9S12ZVM Family Reference Manual Rev. 1.3
256 Freescale Semiconductor
8.3.2.2 S12CPMU_UHV_V6 Synthesizer Register (CPMUSYNR)
The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency
range.
Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
NOTE
Writing to this register clears the LOCK and UPOSC status bits.
NOTE
f
VCO
must be within the specified VCO frequency lock range. Bus
frequency f
bus
must not exceed the specified maximum.
The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct
PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
1
OMRF
Oscillator Clock Monitor Reset Flag — OMRF is set to 1 when a loss of oscillator (crystal) clock occurs. Refer
to 8.5.3, “Oscillator Clock Monitor Reset for details.This flag can only be cleared by writing a 1. Writing a 0 has
no effect.
0 Loss of oscillator clock reset has not occurred.
1 Loss of oscillator clock reset has occurred.
0
PMRF
PLL Clock Monitor Reset Flag — PMRF is set to 1 when a loss of PLL clock occurs. This flag can only be
cleared by writing a 1. Writing a 0 has no effect.
0 Loss of PLL clock reset has not occurred.
1 Loss of PLL clock reset has occurred.
Module Base + 0x0004
7 6 5 4 3 2 1 0
R
VCOFRQ[1:0] SYNDIV[5:0]
W
Reset 0 1 0 1 1 0 0 0
Figure 8-5. S12CPMU_UHV_V6 Synthesizer Register (CPMUSYNR)
Table 8-1. CPMURFLG Field Descriptions (continued)
Field Description
f
VCO
2 f
REF
×
SYNDIV 1
+
( ) ×
=
If PLL has locked (LOCK=1)