Freescale Semiconductor MC9S12ZVM series, Справочное руководство

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Chapter 14 Pulse Width Modulator with Fault Protection (PMF15B6CV3)
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor 549
14.4.12.6 Synchronization Output (pmf_reload)
The PMF uses reload events to output a synchronization pulse, which can be used as an input to the timer
module. A high-true pulse occurs for each PWM cycle start of the PWM, regardless of the state of the
related LDOK bit or global load OK and load frequency.
14.4.13 Fault Protection
Fault protection can disable any combination of PWM outputs (for all FAULT0-5 inputs) or switch to
output control register PMFOUTF on a fault event (for FAULT4-5 only). Faults are generated by an active
level
1
on any of the FAULT inputs. Each FAULT input can be mapped arbitrarily to any of the PWM
outputs.
In complementary mode, if a FAULT4 or FAULT5 event is programmed to switch to output control on a
fault event resulting in a PWM active state on a particular output, then the transition will take place after
deadtime insertion. Thus an asynchronous path to disable the PWM output is not available.
On a fault event the PWM generator continues to run.
The fault decoder affects the PWM outputs selected by the fault logic and the disable mapping register.
The fault protection is enabled even when the PWM is not enabled; therefore, a fault will be latched in and
will be cleared in order to prevent an interrupt when the PWM is enabled.
14.4.13.1 Fault Input Sample Filter
Each fault input has a sample filter to test for fault conditions. After every bus cycle setting the FAULT m
input at logic zero, the filter synchronously samples the input once every four bus cycles. QSMP
determines the number of consecutive samples that must be logic one for a fault to be detected. When a
fault is detected, the corresponding FAULT
m flag, FIF m , is set. FIF m can only be cleared by writing a logic
one to it.
If the FIE m , FAULT m interrupt enable bit is set, the FIF m flag generates a CPU interrupt request. The
interrupt request latch remains set until:
• Software clears the FIF m flag by writing a logic one to it
• Software clears the FIE m bit by writing a logic zero to it
• A reset occurs
14.4.13.2 Automatic Fault Recovery
Setting a fault mode bit, FMOD m , configures faults from the FAULT m input for automatically reenabling
the PWM outputs.
When FMOD m is set, disabled PWM outputs are enabled when the FAULT m input returns to logic zero
and a new PWM half cycle begins. See Figure 14-83 . Clearing the FIF m flag does not affect disabled PWM
outputs when FMOD m is set.
1. The active input level may be defined or programmable at SoC level. The default for internally connected resources is active-
high. For availability and configurability of fault inputs on pins refer to the device overview section.