Freescale Semiconductor MC9S12ZVM series, Справочное руководство

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Chapter 14 Pulse Width Modulator with Fault Protection (PMF15B6CV3)
MC9S12ZVM Family Reference Manual Rev. 1.3
500 Freescale Semiconductor
14.3.2.5 PMF Fault Enable Register (PMFFEN)
4–3
VLMODE
[1:0]
Value Register Load Mode — This field determines the way the value registers are being loaded. This register
cannot be modified after the WP bit is set.
00 Each value register is accessed independently
01 Writing to value register zero also writes to value registers one to five
10 Writing to value register zero also writes to value registers one to three
11 Reserved (defaults to independent access)
2
PINVC
PWM Invert Complement Source Pair C — This bit controls PWM4/PWM5 pair. When set, this bit inverts the
COMPSRCC signal. This bit has no effect in independent mode.
Note: PINVC is buffered. The value written does not take effect until the LDOK bit or global load OK is set and
the next PWM load cycle begins. Reading PINVC returns the value in the buffer and not necessarily the
value in use.
0 No inversion
1 COMPSRCC inverted only in complementary mode
1
PINVB
PWM Invert Complement Source Pair B — This bit controls PWM2/PWM3 pair. When set, this bit inverts the
COMPSRCB signal. This bit has no effect in independent mode.
Note: PINVB is buffered. The value written does not take effect until the LDOK bit or global load OK is set and
the next PWM load cycle begins. Reading PINVB returns the value in the buffer and not necessarily the
value in use.
0 No inversion
1 COMPSRCB inverted only in complementary mode
0
PINVA
PWM Invert Complement Source Pair A — This bit controls PWM0/PWM1 pair. When set, this bit inverts the
COMPSRCA signal. This bit has no effect on in independent mode.
Note: PINVA is buffered. The value written does not take effect until the LDOKA bit or global load OK is set and
the next PWM load cycle begins. Reading PINVA returns the value in the buffer and not necessarily the
value in use.
0 No inversion
1 COMPSRCA inverted only in complementary mode
Address: Module Base + 0x0004 Access: User read/write
(1)
1. Read: Anytime
Write: This register cannot be modified after the WP bit is set
7 6 5 4 3 2 1 0
R 0
FEN5
0
FEN4 FEN3 FEN2 FEN1 FEN0
W
Reset 0 0 0 0 0 0 0 0
Figure 14-7. PMF Fault Enable Register (PMFFEN)
Table 14-9. PMFFEN Field Descriptions
Field Description
6,4-0
FEN[5:0]
Fault m Enable —
This register cannot be modified after the WP bit is set.
0 FAULTm input is disabled
1 FAULTm input is enabled for fault protection
m is 0, 1, 2, 3, 4 and 5
Table 14-8. PMFCFG3 Field Descriptions (continued)
Field Description