Freescale Semiconductor MC9S12ZVM series, Справочное руководство

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Chapter 19 128 KB Flash Module (S12ZFTMRZ128K512V2)
MC9S12ZVM Family Reference Manual Rev. 1.3
700 Freescale Semiconductor
CCIE, IGNSF, WSTAT, FDFD, and FSFD bits are readable and writable, ERSAREQ bit is read only, and
remaining bits read 0 and are not writable.
Offset Module Base + 0x0004
7 6 5 4 3 2 1 0
R
CCIE
0 ERSAREQ
IGNSF WSTAT[1:0] FDFD FSFD
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 19-9. Flash Configuration Register (FCNFG)
Table 19-14. FCNFG Field Descriptions
Field Description
7
CCIE
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see
Section 19.3.2.7 )
5
ERSAREQ
Erase All Request — Requests the Memory Controller to execute the Erase All Blocks command and release
security. ERSAREQ is not directly writable but is under indirect user control. Refer to the Reference Manual for
assertion of the soc_erase_all_req input to the FTMRZ module.
0 No request or request complete
1 Request to:
a) run the Erase All Blocks command
b) verify the erased state
c) program the security byte in the Flash Configuration Field to the unsecure state
d) release MCU security by setting the SEC field of the FSEC register to the unsecure state as defined in
Table 19-9 of Section 19.3.2.2 .
The ERSAREQ bit sets to 1 when soc_erase_all_req is asserted, CCIF=1 and the Memory Controller starts
executing the sequence. ERSAREQ will be reset to 0 by the Memory Controller when the operation is completed
(see
Section 19.4.7.7.1 ).
4
IGNSF
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section 19.3.2.8 ).
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
generated
3–2
WSTAT[1:0]
Wait State control bits — The WSTAT[1:0] bits define how many wait-states are inserted on each read access
to the Flash as shown on
Table 19-15 .Right after reset the maximum amount of wait-states is set, to be later re-
configured by the application if needed. Depending on the system operating frequency being used the number
of wait-states can be reduced or disabled, please refer to the Data Sheet for details. For additional information
regarding the procedure to change this configuration please see
Section 19.4.3 . The WSTAT[1:0] bits should not
be updated while the Flash is executing a command (CCIF=0); if that happens the value of this field will not
change and no action will take place.