Freescale Semiconductor MC9S12ZVM series, Справочное руководство

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Chapter 14 Pulse Width Modulator with Fault Protection (PMF15B6CV3)
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor 517
14.3.2.28 PMF Deadtime B Register (PMFDTMB)
The 12-bit value written to this register is the number of PWM clock cycles in complementary channel
operation. A reset sets the PWM deadtime register to the maximum value of 0x0FFF, selecting a deadtime
of 4095 PWM clock cycles. Deadtime is affected by changes to the prescaler value. The deadtime duration
is determined as follows:
T
DEAD_B
= PMFDTMB / f
PWM_B
= PMFDTMB
×
P
B
×
T
core
Eqn. 14-2
14.3.2.29 PMF Enable Control C Register (PMFENCC)
Address: Module Base + 0x002E Access: User read/write
(1)
1. Read: Anytime. Returns zero if MTG is clear.
Write: Anytime if MTG is set. This register cannot be modified after the WP bit is set.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0
PMFDTMB
W
Reset 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Figure 14-33. PMF Deadtime B Register (PMFDTMB)
Address: Module Base + 0x0030 Access: User read/write
(1)
1. Read: Anytime. Returns zero if MTG is clear.
Write: Anytime if MTG is set. GLDOKC and RSTRTC cannot be modified after the WP bit is set.
7 6 5 4 3 2 1 0
R
PWMENC GLDOKC
0 0 0
RSTRTC LDOKC PWMRIEC
W
Reset 0 0 0 0 0 0 0 0
Figure 14-34. PMF Enable Control C Register (PMFENCC)
Table 14-32. PMFENCC Field Descriptions
Field Description
7
PWMENC
PWM Generator C Enable — If MTG is clear, this bit reads zero and cannot be written.
If MTG is set, this bit when set enables the PWM generator C and the PWM4 and PWM5 outputs. When
PWMENC is clear, PWM generator C is disabled, and the PWM4 and PWM5 outputs are in their inactive states
unless the corresponding OUTCTL bits are set.
After setting this bit a reload event is generated at the beginning of the PWM cycle.
0 PWM generator C and PWM4–5 outputs disabled unless the respective OUTCTL bit is set
1 PWM generator C and PWM4–5 outputs enabled
6
GLDOKC
Global Load Okay C — When this bit is set, a PMF external global load OK defined on device level replaces the
function of LDOKC. This bit cannot be modified after the WP bit is set.
0 LDOKC controls reload of double buffered registers
1 PMF external global load OK controls reload of double buffered registers
2
RSTRTC
Restart Generator C — When this bit is set, PWM generator C will be restarted at the next commutation event.
This bit cannot be modified after the WP bit is set.
0 No PWM generator C restart at the next commutation event
1 PWM generator C restart at the next commutation event