Freescale Semiconductor MC9S12ZVM series, Справочное руководство

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Chapter 7 ECC Generation Module (SRAM_ECCV1)
MC9S12ZVM Family Reference Manual Rev. 1.3
238 Freescale Semiconductor
The single bit ECC error generates an interrupt when enabled. The double bit ECC errors are reported by
the SRAM_ECC module, but handled at MCU level. For more information, see the MMC description.
7.3.1 Aligned 2 and 4 Byte Memory Write Access
During an aligned 2 or 4 byte memory write access, no ECC check is performed. The internal ECC logic
generates the new ECC value based on the write data and writes the data words together with the generated
ECC values into the memory.
7.3.2 Other Memory Write Access
Other types of write accesses are separated into a read-modify-write operation. During the first cycle, the
logic reads the data from the memory and performs an ECC check. If no ECC errors were detected then
the logic generates the new ECC value based on the read and write data and writes the new data word
together with the new ECC value into the memory. If required both 2 byte data words are updated.
If the module detects a single bit ECC error during the read cycle, then the logic generates the new ECC
value based on the corrected read and new write read. In the next cycle, the new data word and the new
ECC value are written into the memory. If required both 2 byte data words are updated. The SBEEIF bit
is set. Hence, the single bit ECC error was corrected by the write access.
Figure 7-9 shows an example of
a 2 byte non-aligned memory write access.
If the module detects a double bit ECC error during the read cycle, then the write access to the memory is
blocked and the initiator module is informed about the error.
1 or 3 byte write,
non-aligned 2
byte write
no 2
read data from the memory
old + new
data
—
write old + new data to the memory
single
bit
2
read data from the memory
cor
new data
SBEEIF
write cor new data to the
memory
double
bit
2
read data from the memory
unchanged
initiator module is
informed
ignore write data
read access
no 1 read from memory unchanged -
single
bit
1
(1)
read data from the memory
corrected
data
SBEEIF
write corrected data back to memory
double
bit
1
read from memory unchanged data mark as invalid
1. The next back to back read access to the memory will be delayed by one clock cycle
Table 7-9. Memory access cycles
Access type
ECC
error
access
cycle
Internal operation
Memory
content
Error indication