SSR<14:13> TXDIS
These bits allow diagnostics to disable the EIA drivers on
the serial lines. When TXDIS are 0’s, the EIA drivers are
active. When TXDIS are 1’s, the EIA drivers are disabled.
Since the TXDIS signals are automatically cleared at power up
or reset, the EIA drivers are enabled by default. TXDIS<0>
disables communication port 1 (serial line 2) and the mouse,
and TXDIS<1> disables communication port 2 (serial line 3)
and the keyboard.
SSR<12>
This bit is reserved.
SSR<11>
This signal can be read from and written to. The SCC UARTS
are placed in a hard reset state when this bit is 0. This bit is
cleared to 0 at power up or reset, resetting the two SCC’s.
SSR<10>
This bit can be read from and written to. The time-of-year
controller is placed in a hard reset state when this bit is 0.
This bit is cleared to 0 at power up or reset, resetting the TOY.
When reset, the TOY loses neither its date nor its 50 bytes of
permanent storage.
SSR<9>
This bit can be read from and written to. The 53C94 SCSI
controller is placed in a hard reset state when this bit is 0. This
bit is cleared to 0 at power up or reset, resetting the 53C94
SCSI controller.
SSR<8>
This bit can be read from and written to. LANCE is placed in
a hard reset state when this bit is 0. This bit is cleared to 0 at
power up or reset, resetting LANCE.
CPU and System Registers
E–19
Содержание DECstation 5000/100 Series
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Страница 55: ...LJ 02972 TI0 MLO 010159 Figure 2 10 System Boot ROM Switches Service Operations 2 19...
Страница 139: ...WS33O125 CPU module CPU module connector Front view Back view Figure 5 6 33 MHz CPU module Base System FRUs 5 11...
Страница 140: ...LJ 02971 TI0 MLO 010159 Figure 5 7 50 MHz R4000 based CPU module 5 12 Base System FRUs...
Страница 151: ...WS33M076 Figure 5 14 Removing a memory module Base System FRUs 5 23...
Страница 153: ...WS33M075 Figure 5 15 Installing a memory module Base System FRUs 5 25...
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