Digital Equipment DECstation 5000/100 Series, Руководство по обслуживанию

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CPU Registers for R4000 Only
Table E-2. R4000 CPU Registers
Register Description
Cause Cause of last exception
EPC Exception program counter
Status Status register
BadVAddr Bad virtual address (read only)
Error EPC Error Exception program counter
Config Configuration register
Cause Register (R3000 Only)
The cause register is a 32-bit read/write register that describes
the nature of the last exception. A 4-bit exception code indicates
the cause of the exception, and the remaining fields contain
detail information relevant to the handling of certain types of
exceptions.
The branch delay (BD) bit indicates whether the EPC was
adjusted to point at the branch instruction that precedes
the next restartable instruction. For a coprocessor unusable
exception, the coprocessor error (CE) field indicates the
coprocessor unit number referenced by the instructions that
caused the exception.
The interrupt pending (IP) field indicates which external,
internal, coprocessor, and software interrupts are pending.
You can write to
1 0
to set or reset software interrupts. The
remaining bits,
7 2
, are read only and represent external,
internal, or coprocessor interrupts.
The number and assignment of the IP bits are implementation
dependent. R3000A processors have six external interrupts,
where IP5 is used for the MIPS floating-point coprocessor
interrupt. IP2 is normally used for system bus (I/O) interrupts.
The cause register has the following format:
CPU and System Registers E–3