Digital Equipment DECstation 5000/100 Series, Руководство по обслуживанию

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System Support Register (SSR)
The SSR can be both read from and written to. Bits <31:16>
are used inside the I/O control ASIC. Bits <15:0> generate
signals visible outside the I/O control ASIC.
Table E-8. System Support Register 0x1C040100
Bits Access Description
31 R/W Communication port 1 transmit DMA enable
(1=enable, 0=disable)
30 R/W Communication port 1 receive DMA enable (1=enable,
0=disable)
29 R/W Communication port 2 transmit DMA enable
(1=enable, 0=disable)
28 R/W Communication port 2 receive DMA enable (1=enable,
0=disable)
27:23 R/W Reserved.
22 R/W Reserved
21 R/W Reserved
20 R/W Reserved
19 R/W Reserved
18 R/W SCSI DMA direction, 0 = transmit (read from
memory)
17 R/W SCSI DMA enable (1=enable, 0=disable)
16 R/W LANCE DMA enable (1=enable, 0=disable)
15 R/W DIAGDN (diagnostic flag)
14:13 R/W TXDIS (serial transmit disable)
12 R/W Reserved
11 R/W SCC reset (active low)
10 R/W RTC reset (active low)
9 R/W 53C94 SCSI controller reset (SCSI active low)
8 R/W LANCE reset (Ethernet active low)
7..0 R/W LEDs
CPU and System Registers E–17