List of Figures
ARM DDI 0301H
Copyright © 2004-2009 ARM Limited. All rights reserved.
xviii
ID012310
Non-Confidential, Unrestricted Access
Figure 3-4
TCM control and configuration registers ..................................................................................... 3-8
Figure 3-5
Cache Master Valid Registers .................................................................................................... 3-9
Figure 3-6
DMA control and configuration registers ..................................................................................... 3-9
Figure 3-7
System performance monitor registers ..................................................................................... 3-10
Figure 3-8
System validation registers ....................................................................................................... 3-11
Figure 3-9
CP15 MRC and MCR bit pattern ............................................................................................... 3-12
Figure 3-10
Main ID Register format ............................................................................................................ 3-20
Figure 3-11
Cache Type Register format ..................................................................................................... 3-21
Figure 3-12
TCM Status Register format ..................................................................................................... 3-24
Figure 3-13
TLB Type Register format ......................................................................................................... 3-25
Figure 3-14
Processor Feature Register 0 format ........................................................................................ 3-26
Figure 3-15
Processor Feature Register 1 format ........................................................................................ 3-28
Figure 3-16
Debug Feature Register 0 format ............................................................................................. 3-29
Figure 3-17
Memory Model Feature Register 0 format ................................................................................ 3-31
Figure 3-18
Memory Model Feature Register 1 format ................................................................................ 3-32
Figure 3-19
Memory Model Feature Register 2 format ................................................................................ 3-34
Figure 3-20
Memory Model Feature Register 3 format ................................................................................ 3-35
Figure 3-21
Instruction Set Attributes Register 0 format .............................................................................. 3-36
Figure 3-22
Instruction Set Attributes Register 1 format .............................................................................. 3-38
Figure 3-23
Instruction Set Attributes Register 2 format .............................................................................. 3-39
Figure 3-24
Instruction Set Attributes Register 3 format .............................................................................. 3-40
Figure 3-25
Instruction Set Attributes Register 4 format .............................................................................. 3-42
Figure 3-26
Control Register format ............................................................................................................. 3-44
Figure 3-27
Auxiliary Control Register format .............................................................................................. 3-49
Figure 3-28
Coprocessor Access Control Register format ........................................................................... 3-51
Figure 3-29
Secure Configuration Register format ....................................................................................... 3-52
Figure 3-30
Secure Debug Enable Register format ..................................................................................... 3-54
Figure 3-31
Non-Secure Access Control Register format ............................................................................ 3-56
Figure 3-32
Translation Table Base Register 0 format ................................................................................ 3-57
Figure 3-33
Translation Table Base Register 1 format ................................................................................ 3-59
Figure 3-34
Translation Table Base Control Register format ....................................................................... 3-61
Figure 3-35
Domain Access Control Register format ................................................................................... 3-63
Figure 3-36
Data Fault Status Register format ............................................................................................. 3-64
Figure 3-37
Instruction Fault Status Register format .................................................................................... 3-66
Figure 3-38
Cache operations ...................................................................................................................... 3-70
Figure 3-39
Cache operations with MCRR instructions ............................................................................... 3-71
Figure 3-40
c7 format for Set and Index ....................................................................................................... 3-72
Figure 3-41
c7 format for MVA ..................................................................................................................... 3-73
Figure 3-42
Format of c7 for VA ................................................................................................................... 3-73
Figure 3-43
Cache Dirty Status Register format .......................................................................................... 3-78
Figure 3-44
c7 format for Flush Branch Target Entry using MVA ................................................................ 3-79
Figure 3-45
PA Register format for successful translation ........................................................................... 3-80
Figure 3-46
PA Register format for aborted translation ................................................................................ 3-80
Figure 3-47
TLB Operations Register MVA and ASID format ...................................................................... 3-87
Figure 3-48
TLB Operations Register ASID format ...................................................................................... 3-87
Figure 3-49
Instruction and data cache lockdown register formats .............................................................. 3-88
Figure 3-50
Data TCM Region Register format ............................................................................................ 3-90
Figure 3-51
Instruction TCM Region Register format ................................................................................... 3-91
Figure 3-52
Data TCM Non-secure Control Access Register format ........................................................... 3-93
Figure 3-53
Instruction TCM Non-secure Control Access Register format .................................................. 3-95
Figure 3-54
TCM Selection Register format ................................................................................................. 3-96
Figure 3-55
Cache Behavior Override Register format ................................................................................ 3-97
Figure 3-56
TLB Lockdown Register format ............................................................................................... 3-100
Figure 3-57
Primary Region Remap Register format ................................................................................. 3-102
Figure 3-58
Normal Memory Remap Register format ................................................................................ 3-103
Figure 3-59
DMA identification and status registers format ....................................................................... 3-106
Figure 3-60
DMA User Accessibility Register format ................................................................................. 3-108
Figure 3-61
DMA Channel Number Register format .................................................................................. 3-109
Figure 3-62
DMA Control Register format .................................................................................................. 3-112
Figure 3-63
DMA Channel Status Register format ..................................................................................... 3-117