Chapter 6: IP Core Interfaces
6–13
Avalon-ST RX Interface
November 2012
Altera Corporation
Arria V GZ Hard IP for PCI Express
shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs
for a four dword header with qword aligned addresses. In this example,
rx_st_empty
is low because data is valid for all 128-bits in the
rx_st_eop
cycle.
illustrates the timing of the RX interface when the Application Layer
backpressures the Hard IP by deasserting
rx_st_ready
. The
rx_st_valid
signal
deasserts within three cycles after
rx_st_ready
is deasserted. In this example,
rx_st_valid
is deasserted in the next cycle.
rx_st_data
is held until the Application
Layer is able to accept it.
Figure 6–12. 128-Bit Avalon-ST rx_st_data Cycle Definition for 4-Dword Header TLPs with Qword Aligned Addresses
pld_clk
rx_st_valid
rx_st_data[127:96]
rx_st_data[95:64]
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_empty
Header3
Data3
Data n
Header 2
Data 2
Data n-1
Header 1
Data 1
Data n-2
Header 0
Data 0
Data n-3
Figure 6–13. 128-Bit Application Layer Backpressures Hard IP Transaction Layer for RX Transactions
pld_clk
rx_st_data[127:0]
rx_st_sop
rx_st_eop
rx_st_empty
rx_st_ready
rx_st_valid
4562 . . .
c19a . . .
0217b . . . 134c . . .
8945 . . .
3458ce. . . 2457ce. . .
000a7896c000bc34...