6–34
Chapter 6: IP Core Interfaces
Completion Side Band Signals
Arria V GZ Hard IP for PCI Express
November 2012
Altera Corporation
the errors in the Configuration Space, and automatically sends error messages in
accordance with the
PCI Express Base Specification
. Note that the Application Layer is
responsible for sending the completion with the appropriate completion status value
for non-posted requests. Refer to
errors that are automatically detected and handled by the Hard IP.
f
For a description of the completion rules, the completion header format, and
completion status field values, refer to Section 2.2.9 of the
.
Table 6–12. Completion Signals for the Avalon-ST Interface (Part 1 of 2)
Signal
I/O
Description
cpl_err[6:0]
I
Completion error. This signal reports completion errors to the Configuration
Space. When an error occurs, the appropriate signal is asserted for one cycle.
■
cpl_err[0]
: Completion timeout error with recovery. This signal should be
asserted when a master-like interface has performed a non-posted request
that never receives a corresponding completion transaction after the 50 ms
timeout period when the error is correctable. The Hard IP automatically
generates an advisory error message that is sent to the Root Complex.
■
cpl_err[1]
: Completion timeout error without recovery. This signal should
be asserted when a master-like interface has performed a non-posted request
that never receives a corresponding completion transaction after the 50 ms
time-out period when the error is not correctable. The Hard IP automatically
generates a non-advisory error message that is sent to the Root Complex.
■
cpl_err[2]
: Completer abort error. The Application Layer asserts this signal
to respond to a non-posted request with a Completer Abort (CA) completion.
The Application Layer generates and sends a completion packet with
Completer Abort (CA) status to the requestor and then asserts this error signal
to the Hard IP. The Hard IP automatically sets the error status bits in the
Configuration Space register and sends error messages in accordance with
the
PCI Express Base Specification, Rev. 2.1
■
cpl_err[3]
: Unexpected completion error. This signal must be asserted
when an Application Layer master block detects an unexpected completion
transaction. Many cases of unexpected completions are detected and reported
internally by the Transaction Layer. For a list of these cases, refer to
“Transaction Layer Errors” on page 13–3
.