Chapter 6: IP Core Interfaces
6–19
Avalon-ST TX Interface
November 2012
Altera Corporation
Arria V GZ Hard IP for PCI Express
tx_st_empty[1:0]
(continued)
2
I
empty
When TLP ends in the upper 128bits, the following equations
apply:
■
tx_st_eop[1]=1 & tx_st_empty[1]=0
,
tx_st_data[255:128]
contains valid data
■
tx_st_eop[1]=1 & tx_st_empty[1]=1
,
tx_st_data[191:128]
contains valid data,
tx_st_data[255:192]
is empty
tx_st_err
1
I
error
Indicates an error on transmitted TLP. This signal is used to
nullify a packet. It should only be applied to posted and
completion TLPs with payload. To nullify a packet, assert this
signal for 1 cycle after the SOP and before the EOP. When a
packet is nullified, the following packet should not be transmitted
until the next clock cycle.
tx_st_err
is not available for packets
that are 1 or 2 cycles long.
For 256-bit data, when you turn on
Enable multiple packets per
cycle
, the following correspondences apply:
■
bit 1 applies to
tx_st_data[255:128]
■
bit 0 applies to
tx_st_data[127:0]
for a timing diagram that
illustrates the use of the error signal. Note that it must be
asserted while the valid signal is asserted.
tx_st_parity
8, 16,
32
O
component
specific
Byte parity is generated when you turn on
Enable byte parity
ports on Avalon-ST interface
on the
System Settings
tab of the
GUI.
Each bit represents odd parity of the associated byte of the
tx_st_data
bus. For example, bit[0] corresponds to
tx_st_data[7:0]
, bit[1] corresponds to
tx_st_data[15:8]
,
and so on.
Component Specific Signals
tx_cred_datafccp
12
O
component
specific
Data credit limit for the received FC completions. Each credit is 16
bytes.
tx_cred_datafcnp
12
O
component
specific
Data credit limit for the non-posted requests. Each credit is 16
bytes.
tx_cred_datafcp
12
O
component
specific
Data credit limit for the FC posted writes. Each credit is 16 bytes.
tx_cred_fchipcons
6
O
component
specific
Asserted for 1 cycle each time the Hard IP consumes a credit. The
6 bits of this vector correspond to the following 6 types of credit
types:
■
[5]: posted headers
■
[4]: posted data
■
[3]: non-posted header
■
[2]: non-posted data
■
[1]: completion header
■
[0]: completion data
During a single cycle, the IP core can consume either a single
header credit or both a header and a data credit.
Table 6–5. 64-, 128-, or 256-Bit Avalon-ST TX Datapath (Part 3 of 4)
Signal
Width
Dir
Avalon-ST
Type
Description