11–6
Chapter 11: Interrupts
Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
Arria V GZ Hard IP for PCI Express
November 2012
Altera Corporation
The RX master module port has as many as 16 Avalon-MM interrupt input signals
(
RXmirq_irq[
<n>
:0]
, where
<n>
15)). Each interrupt signal indicates a distinct
interrupt source. Assertion of any of these signals, or a PCI Express mailbox register
write access, sets a bit in the
Avalon-MM
to
PCI
Express
Interrupt
Status
register.
Multiple bits can be set at the same time; software determines priorities for servicing
simultaneous incoming interrupt requests. Each set bit in the
Avalon-MM
to
PCI
Express
Interrupt
Status
interrupt status register generates a PCI Express interrupt,
if enabled, when software determines its turn. Software can enable the individual
interrupts by writing to the
“Avalon-MM to PCI Express Interrupt Enable Register
through the CRA slave.
When any interrupt input signal is asserted, the corresponding bit is written in the
“Avalon-MM to PCI Express Interrupt Status Register 0x0040” on page 7–13
Software reads this register and decides priority on servicing requested interrupts.
After servicing the interrupt, software must clear the appropriate serviced interrupt
status
bit and ensure that no other interrupts are pending. For interrupts caused by
“Avalon-MM to PCI Express Interrupt Status Register 0x0040” on page 7–13
mailbox
writes, the status bits should be cleared in the
“Avalon-MM to PCI Express Interrupt
Status Register 0x0040” on page 7–13
. For interrupts due to the incoming interrupt
signals on the Avalon-MM interface, the interrupt status should be cleared in the
Avalon-MM component that sourced the interrupt. This sequence prevents interrupt
requests from being lost during interrupt servicing.
Figure 11–7
shows the logic for the entire interrupt generation process.
Figure 11–7. Avalon-MM Interrupt Propagation to the PCI Express Link
SET
CLR
D
Q
Q
Interrupt Disable
(Configuration Space Command Register [10])
Avalon-MM-to-PCI-Express
Interrupt Status and Interrupt
Enable Register Bits
A2P_MAILBOX_INT7
A2P_MB_IRQ7
A2P_MAILBOX_INT6
A2P_MB_IRQ6
A2P_MAILBOX_INT5
A2P_MB_IRQ5
A2P_MAILBOX_INT4
A2P_MB_IRQ4
A2P_MAILBOX_INT3
A2P_MB_IRQ3
A2P_MAILBOX_INT2
A2P_MB_IRQ2
A2P_MAILBOX_INT1
A2P_MB_IRQ1
A2P_MAILBOX_INT0
A2P_MB_IRQ0
AV_IRQ_ASSERTED
AVL_IRQ
MSI Enable
(Configuration Space Message Control Register[0])
MSI Request
PCI Express Virtual INTA signalling
(When signal rises ASSERT_INTA Message Sent)
(When signal falls DEASSERT_INTA Message Sent)