16–2
Chapter 16: Testbench and Design Example
Endpoint Testbench
Arria V GZ Hard IP for PCI Express
November 2012
Altera Corporation
Your Application Layer design may need to handle at least the following scenarios
that are not possible to create with the Altera testbench and the Root Port BFM:
■
It is unable to generate or receive Vendor Defined Messages. Some systems
generate Vendor Defined Messages and the Application Layer must be designed
to process them. The Hard IP block passes these messages on to the Application
Layer which, in most cases should ignore them.
■
It can only handle received read requests that are less than or equal to the
currently set
Maximum payload size
option specified under
PCI Express/PCI
Capabilities
heading under the
Device
tab using the parameter editor. Many
systems are capable of handling larger read requests that are then returned in
multiple completions.
■
It always returns a single completion for every read request. Some systems split
completions on every 64-byte address boundary.
■
It always returns completions in the same order the read requests were issued.
Some systems generate the completions out-of-order.
■
It is unable to generate zero-length read requests that some systems generate as
flush requests following some write transactions. The Application Layer must be
capable of generating the completions to the zero length read requests.
■
It uses fixed credit allocation.
■
It does not support parity.
■
It does not support multi-function designs which are available when using
configuration bypass mode or Single Root I/O Virtualization (RS-IOV).
Endpoint Testbench
After you install the Quartus II software for 11.0, you can copy any of the five example
designs from the
<install_dir>
/ip/altera/altera_pcie/altera_pcie_hip_ast_ed
/example_design
directory. You can generate the testbench from the example design
as was shown in
Chapter 2, Getting Started with the Arria V GZ Hard IP for PCI
.