Chapter 17: Debugging
17–7
Setting Up Simulation
November 2012
Altera Corporation
Arria V GZ Hard IP for PCI Express
Reduce Counter Values for Serial Simulations
You can accelerate simulation by reducing the value of counters whose default values
are set for hardware, not simulation.
Complete the following steps to reduce counter values for simulation:
1. Open
<work_dir>
/
<variant>
/testbench/
<variant>
_tb/simulation/submodules/
altpcie_tbed_sv_hwtcl.v
.
2. Search for the string,
test_in
.
3. To reduce the value of several counters, set
test_in[0] = 1
.
4. Save
altpcie_tbed_sv_hwtcl.v
.
Disable the Scrambler for Gen3 Simulations
The 128b/130b encoding scheme implemented by the scrambler applies a binary
polynomial to the data stream to ensure enough data transitions between 0 and 1 to
prevent clock drift. The data is decoded at the other end of the link by running the
inverse polynomial.
Complete the following steps to disable the scrambler:
1. Open
<work_dir>
/
<variant>
/testbench/
<variant>
_tb/simulation/submodules/
altpcie_tbed_sv_hwtcl.v
.
2. Search for the string,
test_in
.
3. To disable the scrambler, set
test_in[2] = 1
.
4. Save
altpcie_tbed_sv_hwtcl.v
.
Change between the Hard and Soft Reset Controller
The Hard IP for PCI Express includes both hard and soft reset control logic. By
default, Gen1 ES and Gen1 and Gen2 production devices use the Hard Reset
Controller. Gen2 and Gen3 ES devices and Gen3 production devices use the soft reset
controller. For variants that use the hard reset controller, changing to the soft reset
controller provides greater visibility.
Complete the following steps to change to the soft reset controller:
1. Open
<work_dir>
/
<variant>
/testbench/
<variant>
_tb/simulation/submodules/
variant.v
.
2. Search for the string,
hip_hard_reset_hwtcl
.
3. If
hip_hard_reset_hwtcl = 1
, the hard reset controller is active. Set
hip_hard_reset_hwtcl = 0
to change to the soft reset controller.
4. Save
variant.v
.