Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express
2–5
MegaWizard Plug-In Manager Design Flow
November 2012
Altera Corporation
Arria V GZ Hard IP for PCI Express
User Guide
9. .Specify the
Base Address Register and Expansion ROM
settings listed
Table 2–2
.
10. Under the
Base and Limit Registers
heading, disable both the
Input/Output
and
Prefetchable memory
options. (These options are for Root Ports.)
11. Specify the
Device Identification Registers
settings listed in the center column of
Table 2–3
. The right-hand column of this table lists the value assigned to Altera
devices. You must use the Altera values to run the reference design described in
AN 456 PCI Express High Performance Reference Design
. Be sure to use your
company’s values for your final product.
Application Layer interface
Avalon-ST 64-bit
RX buffer credit allocation - performance for
received requests
Low
Reference clock frequency
100 MHz
Use 62.5 MHz Application Layer clock for ×1
Leave this option off
Use deprecated RX Avalon-ST data byte enable
port (rx_st_be)
Leave this option off
Enable configuration via the PCIe link
Leave this option off
Enable byte parity ports on Avalon-ST interface
Leave this option off
Multiple packets per cycle
Leave this option off
Enable configuration via the PCIe link
Leave this option off
Enable Hard IP reconfiguration
Leave this option off
Table 2–2. Base Address Register and Expansion ROM Settings
BAR Number
TYPE
Size
0
64-bit Prefetchable Memory
256 MBytes - 28 bits
1
Disable this BAR
N/A
2
32-bit Non-Prefetchable Memory
1 KByte - 10 bits
3
Disable this BAR
N/A
4
Disable this BAR
N/A
5
Disable this BAR
N/A
Expansion ROM
Disabled
—
Table 2–3. Device Identification Registers
Register Name
Value
Altera Value
Vendor ID
0x00000000
0x00001172
Device ID
0x00000001
0x0000E001
Revision ID
0x00000001
0x00000001
Class Code
0x00000000
0x00FF0000
Subsystem Vendor ID
0x00000000
0x00001172
Subsystem Device ID
0x00000000
0x0000E001
Table 2–1. System Settings Parameters (Part 2 of 2)
Parameter
Value