Chapter 4: Parameter Settings
4–9
MSI and MSI-X Capabilities
November 2012
Altera Corporation
Arria V GZ Hard IP for PCI Express
MSI and MSI-X Capabilities
lists the MSI and MSI-X Capabilities parameter registers.
1
Surprise down
reporting
On/Off
When this option is
On
, a downstream port supports the optional capability of
detecting and reporting the surprise down error condition. This parameter is only
supported for the Arria V GZ Hard IP for PCI Express in Root Port mode.
Slot clock
configuration
On/Off
When
On
, indicates that the Endpoint or Root Port uses the same physical reference
clock that the system provides on the connector. When
Off
, the IP core uses an
independent clock regardless of the presence of a reference clock on the connector.
Table 4–8. Link Capabilities
0x090
(Part 2 of 2)
Parameter
Value
Description
Table 4–9. MSI and MSI-X Capabilities
–
Parameter
Value
Description
MSI messages
requested
1, 2, 4,
8, 16
Specifies the number of messages the Application Layer can request. Sets the
value of the
Multiple Message Capable
field of the
Message Control
register, 0x050[31:16].
Implement MSI-X
On/Off
When
On
, enables the MSI-X functionality.
Bit Range
MSI-X Table size
[10:0]
System software reads this field to determine the MSI-X Table size <
n>
, which is
encoded as <
n
–1>. For example, a returned value of 2047 indicates a table size of
2048. This field is read-only. Legal range is 0–2047 (2
11
). Address:
[26:16]
MSI-X Table Offset
[31:0]
Points to the base of the MSI-X Table. The lower 3 bits of the table BAR indicator
(BIR) are set to zero by software to form a 32-bit qword-aligned offset
. This
field is read-only.
MSI-X Table BAR
Indicator
[2:0]
Specifies which one of a function’s BARs, located beginning at 0x10 in
Configuration Space, is used to map the MSI-X table into memory space. This field
is read-only. Legal range is 0–5.
MSI-X Pending Bit
Array (PBA) Offset
[31:0]
Used as an offset from the address contained in one of the function’s Base
Address registers to point to the base of the MSI-X PBA. The lower 3 bits of the
PBA BIR are set to zero by software to form a 32-bit qword-aligned offset. This
field is read-only.
MSI-X Pending Bit
Array – BAR
Indicator
[2:0]
Indicates which of a function’s Base Address registers, located beginning at 0x10
in Configuration Space, is used to map the function’s MSI-X PBA into memory
space. This field is read-only. Legal range is 0–5.
Note to
(1) Throughout
The Arria V GZ Hard IP for PCI Express User Guide
, the terms word, dword and qword have the same meaning that they have in
the
PCI Express Base Specification Revision 1.0a, 1.1, 2.0 or 2.1
. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.