6–16
Chapter 6: IP Core Interfaces
Avalon-ST RX Interface
Arria V GZ Hard IP for PCI Express
November 2012
Altera Corporation
Multiple Packets per Cycle (256-Bit Interface Only)
If you enable
Multiple Packets Per Cycle
under the
Systems Settings
heading, a TLP
can start on a 128-bit boundary. This mode supports multiple start of packet and end
of packet signals in a single cycle when the Avalon-ST interface is 256 bits wide. It
reduces the wasted bandwidth when a TLP ends in the upper 128-bits of the
Avalon-ST interface because a new TLP can start in the lower 128-bit Avalon-ST
interface. This mode adds complexity to the Application Layer user decode logic.
However, it could result in higher throughput.
Figure 6–18
illustrates this mode for a 256-bit Avalon-ST RX interface. In this figure
rx_st_eop[0]
and
rx_st_sop[1]
are asserted in the same cycle.
Figure 6–18. 256-Bit Avalon-ST RX Interface with Multiple Packets Per Cycle
rx_st_sop[0]
rx_st_eop[0]
rx_st_sop[1]
rx_st_eop[1]
rx_st_data[255:0]
rx_st_be[31:0]
rx_st_bardec1[7:0]
rx_st_bardec2[7:0]
rx_st_empty[1:0]
rx_st_err
rx_st_mask
rx_st_ready
rx_st_valid
.. 12...
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00...
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003458
FF...
FFFFFFFF
00
01
00
FF
FFFFFFFF