Chapter 4 Deployment of the CPU 821xNET
CPU ADAM 821x
4-16
ADAM 8000 Manual CPU 821x – Rev 1.1
When a PLC starts-up, each of the configured interfaces of the CP has to
be synchronized by means of SYNCHRON.
After power is turned on, the CPU 821xNET requires app. 15s for the boot-
procedure. If the PLC should issue a request for synchronization during this
time, an error is returned in the configuration error byte PAFE. This
message is removed when the CP module has completed the boot
process.
The timer in this block is initially set to 20s. Processing will be stopped if the
synchronization is not completed properly within this period.
The following table shows the available block sizes.
Block size
CP block size in byte
0
Use the preset block size
1 16
2 32
3 64
4 128
5 256
6 512
255 512
The sending and receiving blocks SEND and RECEIVE, which initiate the
sending and receiving operations, must be configured in the cycle program
OB1. The blocks SEND_ALL and RECEIVE_ALL perform the actual data-
transfer.
Purely passive connections only require the components SEND_ALL or
RECEIVE_ALL.
To protect the data transfer you should integrate various checkpoints that
evaluate the indicator word.
Synchronization
Cycle
