CPU ADAM 821x
Chapter 6 Deployment of the CPU 821xDP
ADAM 8000 Manual CPU 821x – Rev 1.1
6-5
To guarantee a simultaneous data transfer the V-bus cycle time should al-
ways be same or lower than the DP cycle time.
In the delivered GSD you’ll find the parameter
min_slave_interval = 3ms
.
Thus guarantees that the Profibus data on the V-bus is updated latest
every 3 ms. Though you are allowed to execute one data exchange with
the slave every 3 ms.
Data is referred to as being consistent, if it has the same logical contents.
Data that belongs together is: the high- and low-byte of an analog value
(word consistency) and the control and the status byte with the respective
parameter word required to access the registers.
The data consistency during the interaction between the peripherals and
the controller is only guaranteed for 1 byte. That is, the bits of one byte are
acquired together and they are transmitted together. Byte-wise consistency
is sufficient for the processing of digital signals.
Where the length of the data exceeds a single byte, e.g. analog values, the
data consistency must be expanded. Profibus guarantees consistency for
the required length of data. Please ensure that you use the correct method
to read consistent data from the Profibus master into your PLC.
For additional information please refer to the manual on your Profibus
master as well as the one for the interface module.
If a high-level master fails, this is not recognized automatically by the CPU.
You should always pass along a control byte to indicate the presence of the
master thereby identifying valid master data.
The example at the end of this chapter also explains the use of the control
byte.
There is a wide range of diagnosis functions under Profibus-DP to allow a
fast error localization. The diagnosis data are broadcasted by the bus
system and summarized at the master.
V-bus cycle vs.
DP cycle
Data consistency
Restrictions
Diagnosis
