![background image](http://html1.mh-extra.com/html/york/optiview-yk/optiview-yk_service-instructions-manual_3510350107.webp)
107
FORM 160.54-M1
ISSUE DATE: 10/25/2019
JOHNSON CONTROLS
JCI COMPANY CONFIDENTIAL
7
SECTION 7 - LIQUID CRYSTAL DISPLAY
A 10.4 in. color Liquid Crystal Display, along with
supporting components Display Interface Board and
Backlight Inverter Board are mounted on a plate that is
attached to the OptiView Control Center door. A clear
plexiglass faceplate prevents display surface damage.
System operating parameters are displayed on various
color graphic screens. The various display screens are
selected for display using the keypad keys.
The Display provided in the new chiller or from
YORK as a service replacement part, could be man-
ufactured by any of several approved manufacturers.
Each Display requires a specific Display Interface
Board, Backlight Inverter Board, Inverter Board In-
terface Cable and Program Command Set.
Therefore,
Service replacement Displays or supporting compo-
nents cannot be arbitrarily selected!!!
As explained
below, replacement Displays are provided from YORK
as kits to ensure compatibility of all components. Non-
compatibility of components will result in incorrect
operation!!! See
and
that follow this section. Displays
that could be provided from YORK in new chillers or
as replacement parts are:
• SHARP LQ104V1DG81 (031-03441-000)
• SHARP LQ104V1DG61 (031-02886-000)
• SHARP LQ10D367/368 (031-01774-000)
• LG SEMICON LP104V2-W (031-02046-000)
The YORK part numbers of the Display Interface
Board, Backlight Inverter Board and Inverter Ribbon
Cable provided, are listed on a label attached to the dis-
play mounting plate. These are the part numbers of the
supporting components that are compatible with the
installed display. These supporting components can be
individually replaced. However, if the Liquid Crystal
Display fails, Display Replacement Kit 331-01771-
000 must be ordered as detailed on
page 109
kit contains a replacement Display and all compatible
supporting components.
The Display has 307,200 pixels arranged in a 640 col-
umns X 480 rows matrix configuration. Each pixel con-
sists of 3 windows; red, green and blue, through which
a variable amount of light from the Display Backlight
is permitted to pass through the front of the display.
Imbedded in each window of the pixel is a transistor,
the conduction of which determines the amount of light
that will pass through the window. The conduction of
each transistor is controlled by a signal from the Dis-
play Controller on the microboard. The overall pixel
color is a result of the gradient of red, green and blue
light allowed to pass.
Under Program control, the Display Controller on the
microboard sends a drive signal for each pixel to cre-
ate the image on the display. Each pixel’s drive signal
is an 18 bit binary word; 6 bits for each of the 3 col-
ors, red green and blue. The greater the binary value,
the greater the amount of light permitted to pass. The
columns of pixels are driven from left to right and the
rows are driven top to bottom. To coordinate the drive
signals and ensure that the columns are driven from
left to right and the rows are driven from top to bot-
tom, each drive signal contains a horizontal and verti-
cal sync signal. The
Display Interface Board
receives
these display drive signals from the microboard J5 and
applies them to the Display at connector J1. See
Although there are variations in control signal timing
between different display manufacturers,
depicts typical control signals. Since these
control signals occur at rates greater than can be read
with a Voltmeter, the following description is for infor-
mation only.
There are 480 horizontal rows of pixels. Each row
contains 640 3-window pixels. Beginning with the
top row, the drive signals are applied within each
row, sequentially left to right, beginning with the left
most pixel and ending with the right most pixel. The
rows are driven from top to bottom. The Vertical Sync
(VSYNC) pulse starts the scan in the upper left corner.
The first Horizontal Sync (HSYNC) pulse initiates the
sequential application of RGB drive signals to the 640
pixels in row 1. Upon receipt of the
ENABLE signal,
an RGB drive signal is applied to the first pixel. As
long as the ENABLE
signal is present, RGB drive sig-
nals are then applied to the remaining 639 pixels at the
CLK rate of 25.18MHz, or one every 39.72 nanosec-
onds. Typically it takes 31 microseconds to address all
640 pixels.
Similarly, the next HSYNC pulse applies drive signals
to row 2. This continues until all 480 rows have been
addressed. Total elapsed time to address all 480 rows
is approximately 16 milliseconds. The next VSYNC
pulse causes the above cycle to repeat.