YOKOGAWA WT210, User Manual, Page: 263 / 316

14-47
IM 760401-01E
Communication Commands 2 (System of Commands Complying to the IEEE 488.2-1992 Standard)
14
Operation of the Standard Event Register
The standard event register is provided for eight
different kinds of event which can occur inside the
instrument. Bit 5 (ESB) of the status byte is set to “ 1 ”
when any of the bits in this register becomes “
1
” (or
when the corresponding bit of the standard event
enable register becomes “
1
”).
Examples
1. A query error occurs.
2. Bit 2 (QYE) is set to “ 1 .”
3. Bit 5 (ESB) of the status byte is set to “
1
” if bit 2 of
the standard event enable register is “ 1 .”
It is also possible to check what type of event has
occurred inside the instrument by reading the contents
of the standard event register.
Reading from the Standard Event Register
The contents of the standard event register can be
read by the *ESR command. After completion of the
read-out, the register will be cleared.
Clearing the Standard Event Register
The standard event register is cleared in the following
three cases.
• When the contents of the standard event register
are read using *ESR?
• When the *CLS command is received
• When power is turned ON again
14.4.4 Extended Event Register
Reading the extended event register tells you whether changes in the condition register (reflecting internal conditions)
have occurred. A transition filter can be applied which allows you to decide which events are reported to the
extended event register.
OVR1
6
POV1
7 5 4 3 2 1 0
SRB FOV OVRS ITM ITG UPD POA1
8
OVR2
9
POV2
10
POA2
11
OVR3
12
POV3
13
POA3
14
0
15
6 7 5 4 3 2 1 0 8 9 10 11 12 13 14 15
Condition register
:STATus:CONDition?
Transition filter
0 14 15
Extended event register
1 6 7 5 4 3 8 9 10 11 12 13 2
6 7 5 4 3 2 1 8 9 10 11 12 13 14 15
16
:STATus:FILTer<x>
{RISE|FALL|BOTH|NEVer}
:STATus:EESR?
FILTer<x>
→
The meaning of each bit of the condition register is as follows.
Bit 0 UPD (Updating) Set to “1” during updating of measurement data.
Bit 1 ITG (Integrate busy) Set to “1” during integration. (See figure below)
Bit 2 ITM (Integrate timer busy) Set to “1” during the integration timer is being operated. (See figure on the next page)
Bit 3 OVRS (
∑
results overflow) Set to “1” when the integration results of
∑
overflow. (Display shows “—oF—” )
Bit 4 FOV (Frequency over) Set to “1” when the frequency lies outside the measurement range (Display shows “ErrLo” , “ErrHi” or “FrqEr” .
Bit 5 SRB (Store/Recall busy) Set to “1” while storing or recalling is in progress.
Bit 6 OVR1 (Element 1; measured data over) Set to “1” when the measurement/computed data of element 1 overflow, or when an error occurs. (Display shown “—oF—” ,
“—oL—” , “PFErr” or “dEGEr” )
Bit 7 POV1 (Element 1; voltage peak over) Set to “1” when the voltage value of element 1 exceeds the peak value.
Bit 8 POA1 (Element 1; current peak over) Set to “1” when the current value of element 1 exceeds the peak value.
Bit 9 OVR2 (Element 2; measured data over) Set to “1” when the measurement/computed data of element 2 overflow, or when an error occurs. (Display shown “—oF—” ,
“—oL—” , “PFErr” or “dEGEr” )
Bit 10 POV2 (Element 2; voltage peak over) Set to “1” when the voltage value of element 2 exceeds the peak value.
Bit 11 POA2 (Element 2; current peak over) Set to “1” when the current value of element 2 exceeds the peak value.
Bit 12 OVR3 (Element 3; measured data over) Set to “1” when the measurement/computed data of element 3 overflow, or when an error occurs. (Display shown “—oF—” ,
“—oL—” , “PFErr” or “dEGEr” )
Bit 13 POV3 (Element 3; voltage peak over) Set to “1” when the voltage value of element 3 exceeds the peak value.
Bit 14 POA3 (Element 1; current peak over) Set to “1” when the current value of element 3 exceeds the peak value.
The transition filter is applied to each bit of the condition register seperately, and can be selected from the following. Note that the numbering of the bits used in the filter setting
differs from the actual bit number (1 to 16 vs. 0 to 15).
14.4 Status Report