Toshiba TC32306FTG, Manual

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TC32306FTG
2015-10-01 75
[D5]Noise_DET [Noise Detection]
0: During the detection / Disable
1: Detected (NDET_out Signal = ”H”)
[D4]Pre_DET [Preamble Detection]
0: During the detection / Disable
1: Detected (Preamble_DET_out Signal = ”H”)
[D3:D0]
This output is always “0”.
6.10.23 h’1F Peak Hold Level Monitor
Table 6-78 Register (h’1F)
D7 D6 D5 D4 D3 D2 D1 D0
Name PEAK7 PEAK6 PEAK5 PEAK4 PEAK3 PEAK2 PEAK1 PEAK0
Type R R R R R R R R
[D7:D0]PEAK7..0 [Peak Hold Level Monitor]
The output is 8 bit Peak Hold values of Peak Hold circuit. In FSK, the output this register is the value “b’00000000”.
Notice:
In ASK, the register outputs the values of the Peak Hold Circuit without the function of Data Comparator Quick Charge 2.
6.10.24 h’20 Data Comparator Monitor 1
Table 6-79 Register (h’20)
D7 D6 D5 D4 D3 D2 D1 D0
Name Ref_diff7 Ref_diff6 Ref_diff5 Ref_diff4 Ref_diff3 Ref_diff2 Ref_diff1 Ref_diff0
Type R R R R R R R R
[D7:D0]Ref_diff7..0 [Data Comparator Reference Level Drift Monitor 1]
The output is 8 bit reference level drift of Data Comparator circuit. It is available to monitor for the adjustment for the register
setting of that circuit. The output of 1 LSB will be equivalent to the drift of (1/1.53) kHz. The output this register is the value
"b'11111111" when the drift increase than 165.75kHz. When the Digital Block circuits are disabled, the output of this register is
the value "b'00000000".
6.10.25 h’21 Data Comparator Monitor 2
Table 6-80 Register (h’21)
D7 D6 D5 D4 D3 D2 D1 D0
Name Ref_bias7 Ref_bias6 Ref_bias5 Ref_bias4 Ref_bias3 Ref_bias2 Ref_bias1 Ref_bias0
Type R R R R R R R R
[D7:D0]Ref_bias7..0 [Data Comparator Average Reference Level Monitor]
The output is 8 bit average reference of the Data Comparator circuit. 1 LSB will be equivalent to the average of (1/1.53) kHz × 4
at the setting of FSK. When the Digital Block circuits are disabled, the output of this register is the value "b'00000000".