TC32306FTG
2015-10-01
39
Table 6-39 SPI Mode Timing
Item
Code
Min
Typ.
Max
Unit
CLK Frequency
f
ck
-
-
3.0
MHz
CLK ”H” Time
t
CKWH
100
-
-
ns
CLK ”L” Time
t
CKWL
100
-
-
ns
CLK Setup Time
t
CKS
40
-
-
ns
CLK Hold Time
t
CKH
40
-
-
ns
CLK Rising Time
t
CKR
-
-
10
ns
CLK Falling Time
t
CKF
-
-
10
ns
CS “H” Time
t
CS
40
-
-
ns
CS Setup Time
t
CSS
30
-
-
ns
CS Hold Time
t
CSH
100
-
-
ns
MOSI Setup Time
t
SIS
30
-
-
ns
MOSI Hold Time
t
SIH
30
-
-
ns
MISO Delay Time *
t
SOD
-
-
100
ns
MISO Hold Time *
t
SOH
-
-
100
ns
MISO Disable Time *
t
SOZ
-
-
30
ns
MISO Rising Time *
t
SOR
-
-
50
ns
MISO Falling Time *
t
SOF
-
-
50
ns
* Time values of MISO are derived at the load capacitance of 10pF.
6.7.7 EEPROM Mode
EEPROM and MCU, connect via TC32306FTG. This IC is controlled by the register data of EEPROM.
Select up to 8 configuration that are made as registers' modules from “h'0A” to “h'1C”, depending on
the size of EEPROM. In this mode, use of pins and external connections are different from those of SPI
Mode. For example, TX_SW / RX_SW / ENB pin are used to select configuration of EEPROM. Must not
set MODE2 pin to “L” (= for SPI Mode) at the circuit connection for EEPROM Mode.
Fig 6-23 Conceptual Connection MCU, EEPROM and TC32306FTG
-
In advance, write registers’ values to each configuration data area of EEPROM.
-
MCU commands this IC for selecting configuration data area of EEPROM. (1)
-
This IC read a configuration data from EEPROM by SPI lines at the rising edge of RESET pin
signal. (2)
-
This IC is operated depending on EEPROM data. (3)
- Majority logic
In EEPROM Mode, the majority logic is adopted to reduce the probability of unexpected operation
due to data corruption of EEPROM. Each configuration has 3 sets of data area in EEPROM, and this
IC read them. Then the data values are decided by a majority vote of each bit. In advance, three same
data should be written in each configuration to the specified address of EEPROM. The relation
MCU
MOSI
MISO
CLK
CS
EEPROM
TC32306FTG
TX_SW
RX_SW
ENB
RESET
(1)
(2)
(3)