TC32306FTG
2015-10-01
31
Table 6-31 Deviation Setting (FSK)
h'12[D7]
Dev5
h'12[D6]
Dev4
h'12[D5]
Dev3
h'12[D4]
Dev2
h'12[D3]
Dev1
h'12[D2]
Dev0
n
Deviation after divided (fdev)
315 MHz
nd = 6
434 MHz
nd = 4
868 / 915MHz
nd = 2
0
0
0
0
0
0
0
Unmodulated
Unmodulated
Unmodulated
0
0
0
0
0
1
1
+/-1.67 kHz
+/-2.50 kHz
+/-5.00 kHz
0
0
0
0
1
0
2
+/-3.33 kHz
+/-5.00 kHz
+/-10.00 kHz
0
0
0
0
1
1
3
+/-5.00 kHz
+/-7.50 kHz
+/-15.00 kHz
...
…
…
…
0
0
1
1
0
0
12
+/-20.00 kHz
+/-30.00 kHz
+/-60.00 kHz
...
…
…
…
1
1
1
1
0
1
61
+/-101.67 kHz +/-152.50 kHz
+/-305.00 kHz
1
1
1
1
1
0
62
+/-103.33 kHz +/-155.00 kHz
+/-310.00 kHz
1
1
1
1
1
1
63
+/-105.00 kHz +/-157.50 kHz
+/-315.00 kHz
Deviation after divided: fdev= ( fd / nd)×n
fd: Frequency Resolution of VCO 10kHz (= fosc / 3032) * fosc: Reference Clock Frequency (30.32MHz)
nd: Division Ratio (nd = 6 for 315 MHz Band, nd=4 for 434 MHz Band, nd = 2 for 868 / 915 MHz Band)
n: the value set by register:h'12 [D7:D2]Dev5..0. 0-63 (Converted to decimal.)
6.6.4 ASK Modulation
To select ASK, set register:h’0A[D4] to “1”(ASK). TC32306FTG operates ASK modulation by setting
ON and OFF to RF-Transmitting Power Amplifier (PA) with DATA_IO pin input signal. If PA is
enabled (See Table 6-33.), PA output is shown as table 6-32.
Table 6-32 PA Output and Input Logic (ASK)
DATA_IO Input Logic
PA Output
0
OFF
1
ON
6.6.5 TX Output
PA outputs modulated signal to an antenna.
(1)
RF-Transmitting Power Amplifier (PA)
PA output (PA_OUT pin) is an open drain output. Connect a voltage supply (A_VDD_3V pin) via a
matching circuit. PA is operated by the combination of register:h'0A[D5]RX_TX,
register:h’13[D1]PA_en and internal lock detect signal (LD signal). LD signal is an internal signal only
for PA, and it will keep high level after the first rising edge of PLL_LD signal which is monitored from
DET_TMONI1/2 pin.
Table 6-33 Behavior of PA
h'0A[D5]
RX_TX
h'13[D1]
PA_en
Internal LD
Signal
PA behavior
0
X
X
Disable
1
X
L
Disable
1
0
X
Disable
1
1
H
Enable
X: Don’t care
Internal LD Signal is only use for PA, and the signal keeps "H" after the first rising edge of PLL_LD
Signal. Above function is only available in TX and Internal LD Signal cannot be monitored. To release