TC32306FTG
2015-10-01
68
6.10.14 h’16 RSSI Threshold Setting
Table 6-69 Register (h’16)
D7
D6
D5
D4
D3
D2
D1
D0
Name
DRSSI_Th7 DRSSI_Th6 DRSSI_Th5 DRSSI_Th4 DRSSI_Th3 DRSSI_Th2 DRSSI_Th1 DRSSI_Th0
Initial
0
0
0
0
0
0
0
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[D7:D0]DRSSI_Th7..0 [RSSI Threshold Level of Detection]
- Setting Range
[D7:D0] = 0 - 255 (b’00000000 - b’11111111)
Initial Value: 0
To set RSSI threshold level of detection, refer the value of “h’22[D7:D0] RSSI Level Monitor”.
6.10.15 h’17 Preamble Detector Setting 1
Table 6-70 Register (h’17)
D7
D6
D5
D4
D3
D2
D1
D0
Name
Pre_Time7
Pre_Time6
Pre_Time5
Pre_Time4
Pre_Time3
Pre_Time2
Pre_Time1
Pre_Time0
Initial
1
0
0
1
1
1
1
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
h'18[D7] & h’17[D7:D0]Pre_Time8..0 [Preamble Signal Cycle]
When to set Preamble detection (h’0F[D6]Preamble_en = ”1”), this setting is valid.
- Setting Range
h'18[D7] & h’17[D7:D0] = 0 - 511 (b’000000000 - b’111111111)
Initial Value: 158(b’010011110)
See section 6.5.6 about the Function of Preamble detection.
Notice: The cutoff frequency of Bit Rate Filter is derived from 30.32MHz Reference Clock Frequency.
6.10.16 h’18 Preamble Detector Settings 2
Table 6-71 Register (h’18)
D7
D6
D5
D4
D3
D2
D1
D0
Name
Pre_Time8 Err_Margin6 Err_Margin5 Err_Margin4 Err_Margin3 Err_Margin2 Err_Margin1 Err_Margin0
Initial
0
0
0
0
0
1
0
1
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[D7]Pre_Time8 [Preamble Signal Cycle]
See register h’17.
