TC32306FTG
2015-10-01
29
*nr: Data Comparator Reference Voltage Charge Coefficient
(Set by register:h'1B[D5:D3]Cmp_Ref2..0.)
*nc: Quick Charge Coefficient (Set by register:h'1B[D7:D6]Charge2_Ref1..0.)
Table 6-27 Quick Charge 2
Value of |vi – vref|
Time Constant
Functional Period of Quick Charge 2
|vi - vref|
≥
vth
nr' / fbc
Normal
|vi - vref| < vth
nr / fbc
The threshold level (vi – vref) is set according to FSK deviation. When the threshold level is same or
smaller than that deviation, receiver sensitivity will be worse because of signal noises around the level
of receiver sensitivity. When the threshold level is larger than that deviation, the rising time of signal
will be taken longer. Check signals in User Test to set the threshold level as suitable. The threshold
level is set by register:h'11[D7:D0]Charge2_Th7..0.
- Calculation Example of the threshold level
The case to set register:h'11 [D7:D0]Charge2_Th7..0 = 61 (b’00111101)
61 / 1.53 = 39.9
à
equivalent ±39.9kHz
1.53 is a constant.
(4)
DATA_IO pin control
DATA_IO pin outputs the demodulated signal. DATA_IO pin output can be controlled by the result of
Signal Detection by setting register: h'0F[D3].
Table 6-28 Data_IO Pin Control
h'0A[D5]
RX_TX
h'0F[D3]
Dataout_cnt_en
DET_out Signal
Pin Behavior
0
0
X
Output demodulated signal
0
1
L
à
H
Output demodulated signal
1
X
X
Input pin for TX
X: Don’t care
Notice:
-
The register: h’0F[D3]Dataout_cnt_en is valid in RX.
-
When the register: h’0F[D3] = “1”, TC32306FTG will output demodulated signal from the first
rising edge of DET_out signal. Till the first rising edge of DET_out signal, this IC outputs “L”.
-
When the register:h’0F[D3] = “1” and DET_out signal changes from “L” to “H”, this IC outputs
demodulated signal in spite of the condition of DET_out signal till this IC will be Battery Saving
or Standby mode.
-
When the register:h’0F[D3] = “1” and non use of Signal Detections, this IC doesn’t output
demodulated signal. (Fixed “L” output.)
6.6 RF Transmitter
For RF-Transmitting, set register:h'0A[D5] = "1".