Toshiba TC32306FTG Manual Download Page 7

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TC32306FTG

2015-10-01

Pin No.

Pin Name

I/O

Description

Internal Equivalent Circuit

PLL_REG

Analog

Output

Regulator Output for PLL

Supply to mainly PLL block. Connect a
bypass capacitor.

Do not supply voltage, and do not supply
to an external circuit.

PLL_REG

COM_VDD

150k

100pF

Vref

＋

－

COM_VDD

PLL_GND

Ground(Digital)

X_IN

Analog

Input

Reference Clock Input

Connect crystal oscillator or external
signal generator.

Do not apply a DC bias voltage.

X_IN

PLL_REG

300k

X_OUT

PLL_REG

X_OUT

Analog

Output

Reference Clock Output

Open this pin except a crystal oscillator
use.

Do not apply current or voltage on this pin
from outside. And do not supply the clock
signal to external circuits.

D_REG

Analog

Output

Regulator Output for Digital Block

Supply to mainly digital block. Connect a
bypass capacitor.

Do not apply current or voltage on this pin
from outside. And do not supply to
external circuits.

D_REG

150k

100pF

Vref

＋

－

COM_VDD

Summary of Contents for TC32306FTG

Page 1: ...plications such as tire pressure monitoring system and remote controller etc 3 Features Integrates LNA Mixer IF Filter IF AMP RSSI Signal Detector Bit Rate Filter Data Comparator PLL VCO and PA into a single IC Operating voltage range 2 0 to 3 3 V For 3V Use 2 4V to 5 5V For 5V Use Current consumption TX 12 mA at 10dBm output level RX 9 7 mA Battery Saving 0μA typ Use for four RF Band 315 434 868 ...

Page 2: ... MOSI MISO CLK CS IO_GND DET_TMONI3 DET_TMONI2 DET_TMONI4 ENB RSSI_OUT 3V 5V RX_SW RF_DEC RF_IN A_VDD_3V RF_OUT A_VDD_5V A_REG A_GND IF_REF PA_GND1 PA_OUT PA_GND2 TX_SW RESET MODE2 MODE1 TEST PLL_REG PLL_GND X_IN X_OUT D_REG Reference clock IF AMP PA MIX FSK ASK LNA Limiter 1 RX TX Divider Some of the functional blocks circuits or constants in the block diagram may be omitted or simplified for exp...

Page 3: ...DD 3 ENB Digital Input Enable Pin Select to enable In SPI Mode Address Setting In EEPROM Mode Set a start address to read memory data Notice Do not supply higher voltage than the level of COM_VDD For example in the case of too low no power supply That causes overcurrent at this pin as the ESD protection elements insertion between the pin and the voltage source 3 ENB COM_VDD 4 DET_TMONI4 Analog Out...

Page 4: ...e open this pin 7 RX_SW A_VDD_5V A_VDD_5V 20kΩ 100Ω 1kΩ Digital Input Address Setting In EEPROM Mode Set a start address to read memory data Notice Do not supply higher voltage than the level of COM_VDD For example in the case of too low no power supply That causes overcurrent at this pin as the ESD protection elements insertion between the pin and the voltage source 8 RF_DEC RF Decoupling Pin Con...

Page 5: ...For 5V use voltage regulator output Connect a bypass capacitor Do not apply current or voltage on this pin from outside And do not supply to external circuits except PA_OUT and RF_OUT pin 13 A_REG Analog Output Regulator Output for Analog Block Supply to mainly analog block Connect a bypass capacitor Do not apply current or voltage on this pin from outside And do not supply to external circuits A_...

Page 6: ...ng In EEPROM Mode Set a start address to read memory data Notice Do not supply higher voltage than the level of COM_VDD For example in the case of too low no power supply That causes overcurrent at this pin as the ESD protection elements insertion between the pin and the voltage source 20 RESET Digital Input Reset Initialize TC32306FTG RESET 20 21 MODE2 Digital Input Mode Control Select SPI Mode S...

Page 7: ...rystal oscillator or external signal generator Do not apply a DC bias voltage X_IN PLL_REG 300kΩ X_OUT PLL_REG 26 27 27 X_OUT Analog Output Reference Clock Output Open this pin except a crystal oscillator use Do not apply current or voltage on this pin from outside And do not supply the clock signal to external circuits 28 D_REG Analog Output Regulator Output for Digital Block Supply to mainly dig...

Page 8: ...t Mode EEPROM User Test Mode Notice Do not supply higher voltage than the level of COM_VDD For example in the case of too low no power supply That causes overcurrent at this pin as the ESD protection elements insertion between the pin and the voltage source CLK Control COM_VDD COM_VDD 30 Control Digital Output SPI Clock Output In EEPROM Mode 31 MOSI Digital Input Serial Data Input In SPI Mode SPI ...

Page 9: ...ted signal output at RF Receiving Behavior of this pin is different for each state of TC32306FTG reset See Table 5 2 Notice Output resistance of this pin is 10kΩ when the output drive setting is Low Select proper resistance value of pull up or pull down resistor to get enough output level of the pin when the output drive setting is Low Or select that the output drive setting is High depending on t...

Page 10: ...utput IN IN MISO Z Z Z Z Z Z ENB IN IN IN IN IN IN TX_SW Pull Down Pull Down IN IN IN IN RX_SW Pull Down Pull Down IN IN IN IN DATA_IO Z Low Output Z Low Output Z Low Output DET_TMONI1 2 Low Output Low Output Low Output Low Output Low Output Low Output DET_TMONI3 4 Z Z Z Z Z Z Z High Impedance Notice In SPI Mode TC32306FTG accepts the input of SPI settings at RESET L but will not act In Battery Sa...

Page 11: ...y Input 5V Supply Input COM_VDD 3V Supply Input 5V Supply Input 6 1 1 3V Use At 3V use connect 3V 5V pin to ground Connect COM_VDD pin A_VDD_3V pin and A_VDD_5V pin to a stable 3V supply Notice Must not operate A_REG30 regulator for 5V use Must not connect COM_VDD pin to voltage supply out of range of VDD 3V shown as Table 8 1 This figure is conceptual Select bypass capacitors in application circu...

Page 12: ...n This figure shows main supply ground lines of functional blocks Fig 6 3 Conceptual Supply Ground Connection to Functional Blocks 6 2 Control Mode Settings TC32306FTG has two control modes SPI Serial Peripheral Interface Mode and EEPROM Mode The control mode settings are selected by MODE2 pin User Test Mode in each Control Mode is selected by MODE1 pin A_VDD_3V A_VDD_5V COM_VDD 3V 5V 5V A_REG30 5...

Page 13: ...ode EEPROM Mode Output This IC is master controls EEPROM Input This IC is master reads EEPROM data Input For EEPROM configuration settings EEPROM User Test Mode Input This IC is slave controlled by MCU Output This IC is slave controlled by MCU 6 2 1 SPI Mode Setting and Connection MCU and TC32306FTG are connected by SPI lines and MCU controls this IC Fig 6 4 Conceptual Connection MCU and TC32306FT...

Page 14: ...l the settings except some settings About I O behaviors at Reset status see Table 5 2 H Battery Saving Standby Run by this IC settings In EEPROM Mode ENB pin TX_SW pin RX_SW pin are available Notice Must be reset after voltage supply The value of registers is initialized immediately after reset is released See Table 5 2 of I O behavior at the register initialized In SPI Mode TC32306FTG stays Batte...

Page 15: ...n those status are controlled by two registers h 0A D7 h 0A D6 and ENB pin In EEPROM Mode ENB pin is used for configuration setting Table 6 6 IC Status in SPI Mode MODE2 Pin ENB Pin h 0A D7 ENB h 0A D6 ACT Status Description L L X X Battery Saving The lowest current consumption status TC32306FTG only can accept control data register setting and control settings and they can be changed The transiti...

Page 16: ...A D7 ENB h 0A D6 ACT keep the value 1 6 3 3 Output Drive Settings Select output drive setting at DATA_IO pin MISO pin DET_TMONI1 pin DET_TMONI2 pin by setting registers h 0D D3 DATA_IO_D h 0D D2 MISO_D h 0D D1 TMONI_D The settings become valid when reset is released RESET H Table 6 8 Output Drive Settings h 0D D3 DATA_IO_D DATA_IO pin drive setting h 0D D2 MISO_D MISO pin drive setting h 0D D1 TMO...

Page 17: ...of overall Detection judgment depending on RSSI detection Noise detection and or Preamble detection L NOT determine Signal Detection H Determine Signal Detection Set register h 10 D2 DET_out_cnt_en 1 TC32306FTG holds DET_out output level H after first Signal Detection Table 6 11 DET_out Signal Settings h 10 D2 DET_out_cnt_en DET_out Signal 0 Sequential updating 1 Hold output level H after first Si...

Page 18: ...ection Table 6 12 Logic of DET_out Un_DET_out Signal Detection No Detection RSSI Detection Signal Noise Detection Signal Preamble Detection Signal DET_out Signal RSSI Detection Signal Noise Detection Signal Preamble Detection Signal Un_DET_out Signal H H H H L L H H L OFF H H OFF H L H L OFF L H L OFF OFF H OFF H L OFF H L OFF L OFF OFF L L L OFF L H OFF L OFF H L OFF L OFF L OFF OFF L OFF L H Sig...

Page 19: ...T Pin and keep input signal level range from 0 5 V to 1 5 V Peak to peak Don t supply reference clock signal to external circuit from X_OUT pin Fig 6 7 Case of Reference Clock Circuit 6 4 3 Local Oscillation Local oscillator block consists of the fractional N PLL VCO and frequency divider Local frequency is the output of frequency divider Select the division ratio for expected frequency band Set r...

Page 20: ...Local Frequency RF Transmitting Frequency VCO Frequency Division Ratio Example RF Frequency 314 94MHz Division Ratio 6 Select 315MHz band Transmitting Local Frequency 314 94MHz 1889 64MHz 6 6 5 RF Receiver For RF Receiving set register h 0A D5 0 6 5 1 RF Receiving Abstract Table 6 15 Receiving Function Abstracts Item Function RF Receiving Frequency Band 315 434 868 915 MHz IF Frequency IF 230kHz s...

Page 21: ...alues at 315 MHz Fig 6 9 Receiver Gain Distribution RF_IN pin is input of LNA Input a RF signal via a suitable matching network RF_OUT pin is output of LNA and open drain output Supply voltage via a matching network See the Evaluation Circuit for both input and output matching network About RF_DEC pin connect a capacitor 1000 pF typ and resister 100 Ω typ such as Fig 6 10 Typical LNA Network RF_DE...

Page 22: ... register h 0A D4 Depending upon a type of demodulation IF filter output signal has different path RF detection and additional functions Table 6 18 Demodulations h 0A D5 RX_TX h 0A D4 FSK_ASK Status 0 0 FSK RX 0 1 ASK RX 1 XX TX XX About TX see Table 6 30 6 5 6 FSK Demodulation To select FSK set register h 0A D4 to 0 FSK 1 NIR Near Interference Rejection Filter Select the filter Enable Disable by ...

Page 23: ...filter is depending on the detection of the interference for continuous RX h 1C D1 NIR_L1 1 h 1C D2 NIR_2L0 0 h 13 D0 NIR_H1 0 h 12 D1 NIR_2H0 1 h 1C D0 NIR_L0 0 h 1A D0 NIR_H0 0 1 h 0F D0 NIR_L2 0 h 1B D0 NIR_2L1 1 h 0D D0 NIR_H2 0 h 12 D0 NIR_2H0 0 Pulse Count Detection NIR filter is always valid h 1C D1 NIR_L1 0 h 1C D2 NIR_2L0 1 h 13 D0 NIR_H1 0 h 12 D1 NIR_2H1 0 h 1C D0 NIR_L0 0 h 1A D0 NIR_H...

Page 24: ...tions in FSK Item RSSI Detection Noise Detection Preamble Detection Method Monitoring integrated signal level at IF AMP Monitoring noise level near 34 kHz in FSK demodulation signal Monitoring preamble signal at Data COMP output Data pattern 10101 Signal Detection Enable Disable h 0F D7 Drssi_en 0 Disable 1 Enable h 0F D5 Ndet_en 0 Disable 1 Enable h 0F D6 Preamble_en 0 Disable 1 Enable Detection ...

Page 25: ...h Frequency Signal is occupied in the full of RSSI Noise detection interval the register of Noise Signal Level Monitor h 23 D7 D0 DNDET7 0 outputs d 81 Noise Addition for High Frequency Signal can be valid in Pulse Count Detection and Delay Detection Noise Addition for High Frequency Signal can be valid even if High Frequency Detector is not valid in Delay Detection B Additional Note of Preamble D...

Page 26: ...alid to use the function of Data Comparator Quick Charge 2 This is only valid to use the function of Data Comparator Quick Charge 2 in the subsequent Data Comparator circuit RSSI signal voltage through LPF is kept over the internal setting value in Limiter circuit Limit level is calculated with the peak voltage in the sequential The peak voltage is detected in Peak Hold Circuit in the subsequent o...

Page 27: ... Set it to consider the influence of LPF FSK fc 20kHz ASK fc 40 kHz of the previous circuit Table 6 25 Settings of Bit Rate Filter and Cutoff Frequency including LPF h 0E D4 BRF_Bit3 h 0E D3 BRF_Bit2 h 0E D2 BRF_Bit1 h 0E D1 BRF_Bit0 Cutoff Frequency fc Cutoff Frequency including the previous LPF Internal Clock fbc FSK ASK 0 0 0 0 19 8 kHz 14 1 kHz 17 8 kHz 758 kHz 0 0 0 1 14 0 kHz 11 5 kHz 13 2 k...

Page 28: ... from DET_TMONI3 or 4 pin Because the time constant set by Data Comparator Reference Voltage Charge Coefficient h 1B D5 D3 Cmp_Ref2 0 is slower than the signal data rate the rising time of the signal will be taken long Data Comparator output voltage will reach 90 of vref with nr fbc x 2 30 To shorten rising time of the signal use the function of Data Comparator Quick Charge 1 or 2 2 Data Comparato...

Page 29: ... D0 Charge2_Th7 0 61 b 00111101 61 1 53 39 9 à equivalent 39 9kHz 1 53 is a constant 4 DATA_IO pin control DATA_IO pin outputs the demodulated signal DATA_IO pin output can be controlled by the result of Signal Detection by setting register h 0F D3 Table 6 28 Data_IO Pin Control h 0A D5 RX_TX h 0F D3 Dataout_cnt_en DET_out Signal Pin Behavior 0 0 X Output demodulated signal 0 1 L à H Output demodu...

Page 30: ...mitter Block Diagram 6 6 2 RF Signal Modulation TC32306FTG is available 2 modulation FSK and ASK to be set by register h 0A D4 Table 6 30 RF Signal Modulation h 0A D5 RX_TX h 0A D4 FSK_ASK Modulation 0 XX RX 1 0 FSK TX 1 1 ASK TX XX About RX see Table 6 18 6 6 3 FSK Modulation To select FSK set register h 0A D4 to 0 FSK TC32306FTG operates FSK modulation at PLL block with DATA_IO pin input signal ...

Page 31: ...o 1 ASK TC32306FTG operates ASK modulation by setting ON and OFF to RF Transmitting Power Amplifier PA with DATA_IO pin input signal If PA is enabled See Table 6 33 PA output is shown as table 6 32 Table 6 32 PA Output and Input Logic ASK DATA_IO Input Logic PA Output 0 OFF 1 ON 6 6 5 TX Output PA outputs modulated signal to an antenna 1 RF Transmitting Power Amplifier PA PA output PA_OUT pin is a...

Page 32: ... not be set to TX Must not change RF Transmitting Frequency Band register h 0A D1 D0 alone during TX It may cause of unexpected radiation because the keeping of Internal LD Signal level is not released 2 Output level The output level is controlled 2 types of step Coarse Fine independently by register Table 6 34 Example of PA Output Level Coarse h 13 D3 TX_gain1 h 13 D2 TX_gain0 Output Level Variat...

Page 33: ...NB pin Control Method SPI Single Read Write Burst Read Write EEPROM Control Mode Normal User Test 6 7 2 SPI Mode MCU and TC32306FTG are connected by SPI lines and MCU controls this IC Fig 6 13 Conceptual Connection of SPI Control In SPI Mode TC32306FTG is available Single Read Write and Burst Read Write These are selected from SPI instruction data 10 5 0 5 10 15 TX Output Power dBm h 13 D7 D4 TX_s...

Page 34: ... Data Format In SPI Mode Single Burst Write Read and Confirmation of written data are set by instruction data Enter each SPI control data sequentially from most significant bit MSB Table 6 38 Type of SPI Instructions and Settings SPI Control I7 I6 I5 I4 I3 I2 I1 I0 Single Read Write Write 0 0 0 0 X 1 1 0 Read 0 0 0 0 X 1 1 1 Burst Read Write Write 0 0 0 0 X 0 1 0 Read 0 0 0 0 X 0 1 1 Confirmation ...

Page 35: ...ISO pin outputs 8 bit data from the specified register After output that 8 bit data repeat above routine to read other address data continuously During data read from MISO pin MOSI pin does not accept input data MISO pin outputs the register data when CS pin is L and CLK signal is at the falling edge Fig 6 16 Read Format SPI Single Read Write CLK CS Instruction Address AD0 AD1 AD2 AD3 AD4 AD5 AD6 ...

Page 36: ... to be H in the burst Read Write 2 Read This function continuously reads data to the order from the specified address Set the burst Read Write Read data pattern to the instruction area Set to start register address to the next 8 bit to read that data After input the address MISO pin outputs 8 bit data from the specified register To stop or finish reading data set CS pin to be H Fig 6 18 Read Forma...

Page 37: ...ad Write Confirmation of written data data pattern to the register instruction area Set same as the Burst Read Write Write and input The input data is output from MISO pin with 8 bit delay after the address area The data writing is valid till the rising edge of CS signal and the data reading is finished at the rising edge of CS signal Fig 6 19 Confirmation of Written Data Format SPI Burst Read Wri...

Page 38: ...Timing Burst Read Write The timing chart for explaining the operation of features and may have been simplified CS CLK MOSI MISO Data Input Timing tCS tCSS tCKS tCKWH tCKWL tSIS tSIH tCSH tCKH High Impedance CS CLK MOSI MISO Data Output Timing tCSH tCKH tSOD tSOH tCKF tCKR tSOR tSOF tSOZ LSB CS CLK MOSI MISO Data Output Timing tCSH tCKH tSOD tSOH tCKF tCKR tSOR tSOF tSOZ LSB ...

Page 39: ... and external connections are different from those of SPI Mode For example TX_SW RX_SW ENB pin are used to select configuration of EEPROM Must not set MODE2 pin to L for SPI Mode at the circuit connection for EEPROM Mode Fig 6 23 Conceptual Connection MCU EEPROM and TC32306FTG In advance write registers values to each configuration data area of EEPROM MCU commands this IC for selecting configurati...

Page 40: ...on change is available all the time however the operation is valid at the timing of change of RESET pin from L to H 2 TC32306FTG operates Burst Read to the first set data area of EEPROM through SPI lines Burst Read operates from the start address till the end address of the configuration data sequentially After the reading this IC starts to Run as the configuration of first set data area 3 This IC...

Page 41: ... 169 170 171 183 184 185 186 Config 4 0 1 1 1st 192 193 194 195 207 208 209 210 2nd 212 213 214 215 227 228 229 230 3rd 232 233 234 235 247 248 249 250 Config 5 1 0 0 1st 256 257 258 259 271 272 273 274 2nd 276 277 278 279 291 292 293 294 3rd 296 297 298 299 311 312 313 314 Config 6 1 0 1 1st 320 321 322 323 335 336 337 338 2nd 340 341 342 343 355 356 357 358 3rd 360 361 362 363 375 376 377 378 Co...

Page 42: ...iming chart for explaining the operation of features and may have been simplified CS tCSD RESET tCSWH tCSWH 1 2 3 This IC repeats three times to read configuration data from the EEPROM for the majority logic CS CLK MOSI MISO tCKD tCSD tCKWH tCKWL tMOS tMOD MSB OUT tCKF tCKR RESET LSB OUT tMOD tMOS 1 CS CLK MOSI MISO tCKWH tCKWL tCSH tCKF tCKR MSB IN LSB OUT LSB IN tCSH tMID tMIH 1 tMIS ...

Page 43: ...me tCKWH 150 ns CLK L Time tCKWL 150 ns CLK Rising Time tCKR 50 ns CLK Falling Time tCKF 50 ns CLK Delay Time tCKD 150 ns CS Delay Time tCSD 400 ns CS H Time tCSWH 500 ns CS Hold Time tCSH 100 ns MOSI Preceding Time tMOS 50 ns MOSI Delay Time tMOD 50 ns MISO Delay Time tMID 120 ns MISO Setup Time tMIS 10 ns MISO Hold Time tMIH 100 ns Time values of CLK MISO and MOSI are derived at the load capacit...

Page 44: ...15 D5 MONI3_SEL1 h 15 D4 MONI3_SEL0 Signal MODE1 Pin Battery Saving X X X X Z Run Standby 0 and L X X X L Output Run Standby 1 or H 0 0 0 Data_compREF Run Standby 1 or H 0 0 1 BRF_in Run Standby 1 or H 0 1 0 BRF_out Run Standby 1 or H 0 1 1 DRSSI_out Run Standby 1 or H 1 0 0 Noise _out Run Standby 1 or H 1 0 1 Peak_out Run Standby 1 or H 1 1 0 L Output Run Standby 1 or H 1 1 1 L Output X Don t car...

Page 45: ... and Settings EEPROM Control I7 I6 I5 I4 I3 I2 I1 I0 Single Read Write Write 1 0 0 0 x 1 1 0 Read 1 0 0 0 x 1 1 1 Burst Read Write Write 1 0 0 0 x 0 1 0 Read 1 0 0 0 x 0 1 1 Confirmation of written data 1 0 0 0 x 1 0 1 SPI Function Stop Except above data x 0 or 1 SPI Function Stop After writing SPI instruction data subsequent data input will be disabled Again to enable the input data enter SPI ins...

Page 46: ...0 X X X 105 5μs 1 0 0 0 105 5μs 1 0 0 1 211 1μs 1 0 1 0 316 5μs 1 0 1 1 527 5μs 1 1 0 0 949 5μs 1 Except Above 105 5μs X Don t care Notice Delay is derived from 30 32MHz Reference Clock Frequency In SPI Mode the initial register setting is h 0D D7 Delay_en 0 Delay is always about 105 5 μs In SPI Mode to enter the setup sequence with setting Delay time move TC32306FTG status from Battery Saving Sta...

Page 47: ...ed each other unexpected operation may occur To avoid above make the SPI speed too fast enough to communicate or select the previous way as in Fig 6 29 Check the relationship between supply voltage and reset when to utilize the power on reset during boot sequence See the notice in 6 3 1 Example of Boot Sequence 2 TX in SPI Mode The following Fig 6 30 shows status transition from Battery Saving Sta...

Page 48: ... 6 Input the signal for modulation to DATA_IO pin The RF modulated Signal will be transmitted from PA after PLL_LD signal turns to be H immediately because initial value of register h 13 D1 PA_en is 1 It is also possible to set the register h 13 D1 PA_en 0 at the first register setting Fig 6 30 Example of Boot Sequence Timing Chart SPI Mode TX The example of timing chart may be omitted or simplifi...

Page 49: ... of first set data area of EEPROM sequentially It is indicated by the combination of TX_SW pin RX_SW pin and ENB pin 3 Start to operate with Standby despite of the value of the register h 0A D6 ACT Internal regulators and Reference Clock Oscillator start to operate 4 Read the second and third set data area continuously then the register setting is fixed 5 Continue to operate depending on the setti...

Page 50: ... Fig 6 32 1 At the end of RX set the register h 0A D5 RX_TX 1 then TC32306FTG changes to TX 2 After finishing all register settings for TX and CS pin is set to H this IC starts the setup sequence and PLL lock up then this IC is operated with setting registers 3 At the end of TX set the register h 0A D5 RX_TX 0 then this IC changes to RX After finishing all register settings for RX and CS pin is se...

Page 51: ... ACT will not change Output and check Status_MONI signal at DET_TMONI1 pin and or DET_TMONI2 pin to confirm the transition to Battery Saving by this function About the pins behavior at the transition to Battery Saving by AutoOff see Table 5 2 Table 6 49 AutoOff Function Settings and Status h 10 D5 AutoOffA_en h 10 D4 AutoOffB_en AutoOff Type A AutoOff Type B Status 0 0 OFF OFF 0 1 OFF ON Move to B...

Page 52: ...ff Type A set TC32306FTG status to Battery Saving or Standby by setting new registers and or change RESET ENB pin To use AutoOff Type A again in the continuing RX set this IC status to Battery Saving or Standby by setting new registers and or change RESET ENB pin 2 AutoOff Type B AutoOff by Timer Setting TC32306FTG will move from Run to Battery Saving if the determination of Signal Detection DET_o...

Page 53: ...he starting of timer countdown before RX In the continuing RX the stopping timer countdown of AutoOff Type B is not released even if register settings of RX operation are entered again To use AutoOff Type B again moving to Battery Saving or Standby is needed In this case the timer of AutoOff Type B is surely reset In EEPROM Mode the setting of the timer period is only 275 6 ms and cannot be set ot...

Page 54: ... Setting h 13 0 0 0 1 0 0 1 1 R W TX PA Settings h 14 0 0 0 1 0 1 0 0 R W Monitor Settings1 h 15 0 0 0 1 0 1 0 1 R W Monitor Settings2 h 16 0 0 0 1 0 1 1 0 R W RSSI Threshold Setting h 17 0 0 0 1 0 1 1 1 R W Preamble Detector Setting 1 h 18 0 0 0 1 1 0 0 0 R W Preamble Detector Settings 2 h 19 0 0 0 1 1 0 0 1 R W Noise Detector Threshold Setting h 1A 0 0 0 1 1 0 1 0 R W Signal Detector Settings h ...

Page 55: ...ess Software Reset h 09 D7 D0 Reset Reset is Released Output Current Drive Setting h 0D D3 D1 Status Control 1 h 0A D7 Buttery Saving Run Standby Status Control 2 h 0A D6 Standby Run à See next table Notice h 09 shows register s byte is 09 by hexadecimal and D7 D0 shows bit number are from the 7th to the 0 ...

Page 56: ... D5 RX LNA Gain h 0E D7 D6 IF Filter Bandwidth h 0E D5 Demodulation à See next table Bit Rate Filter Cutoff Frequency h 0E D4 D1 Data Comparator Reference Voltage Charge Coefficient h 1B D5 D3 Data Comparator Quick Charge 1 Enable Disable h 10 D7 Data Comparator Quick Charge 2 Enable Disable h 10 D6 Disable Enable Quick Charge Coefficient h 1B D7 D6 Quick Charge 2 Threshold Level h 11 D7 D0 DATA_I...

Page 57: ...D7 D6 Noise Addition by High Frequency Detector h 19 D0 RSSI Detection Enable Disable h 0F D7 Disable Enable Threshold Level of Detection h 16 D7 D0 Detection Interval h 1A D7 D6 Preamble Detection Enable Disable h 0F D6 Disable Enable Preamble Signal Cycle h 17 D7 D0 h 18 D7 Error Margin h 18 D6 D0 Number of Times for Judgment h 1A D4 D3 Detection Trigger h 1A D2 ASK Data Comparator Quick Charge ...

Page 58: ...is register and register D6 result as the right table In SPI Mode ENB pin H leads these settings are valid and ENB pin L leads TC32306FTG is Battery Saving Status D7 ENB D6 ACT Status 0 X Battery Saving 1 0 Standby 1 1 Run X Don t care D6 ACT Status Control 2 The combinations of this register and register D7 result as the right table In SPI Mode ENB pin H leads these settings are valid and ENB pin...

Page 59: ... 30 32MHz 9 53 x 30 32MHz 10kHz 1016 NC 9 à NC b 1001 Binary FC 1016 à FC b 001111111000 Two s complement format Example2 RX frequency frx and TX frequency ftx are set as follows frx fvco nd f_if NC 53 x fosc FC x fstep nd f_if ftx fvco nd NC 53 x fosc FC x fstep nd frx RX frequency ftx TX frequency f_if IF frequency 230 or 280 kHz nd Division Ratio nd 6 at 315MHz Band nd 4 at 434MHz Band nd 2 at ...

Page 60: ...fvco fosc NC 53 x fosc fstep 1735 68MHz 30 32MHz 4 53 x 30 32MHz 10kHz 744 NC 4 à NC b 0100 Binary FC 744à FC b 00101110100 Two s complement format By using those NC and FC fvco and ftx can be calculated again fvco NC 53 x fosc FC x fstep 4 53 x 30 32MHz 744 x 10kHz 1735 68MHz ftx fvco nd 1735 68MHz 4 433 92MHz Notice The change of fosc results the change of fvco in the same NC and FC 6 10 4 h 0C ...

Page 61: ...ime 105 5μs Notice To start TC32306FTG with this delay time changing the status from Battery Saving Standby to Run after setting this register If this register is set during Run this register setting will be valid after the next transition from Battery Saving Standby to Run D3 DATA_IO_D DATA_IO Output Drive Setting 0 Low 1 High D2 MISO_D MISO Output Drive Setting 0 Low 1 High D1 TMONI_D DET_TMONI1...

Page 62: ..._en Noise Detection 0 Disable 1 Enable D4 Hdet_en High Frequency Detector In Delay Detection h 10 D0 Sel_Det 0 this register setting is valid 0 Disable 1 Enable D3 Dataout_cnt_en DATA_IO Control 0 Disable 1 Enable D2 Digital_en Digital Block Control Digital Block Detctor LPF ASK LPF FSK BRF Data COMP Control 0 Disable 1 Enable D1 Det_reset_n Detection Reset RSSI Detection Noise Detection Preamble ...

Page 63: ...e2_en Data Comparator Quick Charge 2 0 Disable 1 Enable D5 AutoOffA_en AutoOff Type A 0 Disable 1 Enable Notice When to use the function of AutoOff Type A with using Preamble Detection set both Data Comparator Quick Charge 1 and 2 to the status of ON D4 AutoOffB_en AutoOff Type B 0 Disable 1 Enable D3 USER_TEST User Test 0 Disable 1 Enable Internal monitor signals output from DET_TMONI3 DET_TMONI4...

Page 64: ... 10 h 12 TX Deviation Setting Table 6 65 Register h 12 D7 D6 D5 D4 D3 D2 D1 D0 Name Dev5 Dev4 Dev3 Dev2 Dev1 Dev0 NIR_2H1 NIR_2H0 Initial 0 0 1 1 0 0 0 0 Type R W R W R W R W R W R W R W R W D7 D2 Dev5 0 Deviation This deviation depends on the setting of RF frequency band Setting Range D7 D2 0 63 b 000000 111111 Initial Value 12 b 001100 Deviation Setting Range at 30 32MHz Reference Clock Frequenc...

Page 65: ... D2 b 00 Minimum D3 D2 b 11 Maximum Notice In ASK and FSK Receiving settings of register h 13 D7 D2 are invalid D1 PA_en PA Enable Disable The combination register h 0A D5 RX_TX and Internal LD Signal The result of PLL lock detection see below results the operation of PA in the below table h 0A D5 RX_TX D1 PA_en Internal LD Signal PA Function 0 X X Disable 1 X L Disable 1 0 X Disable 1 1 H Enable ...

Page 66: ...of RSSI detection 1 0 0 NDET_out The result of Noise detection 1 0 1 Status_MONI TC32306FTG status Standby Run Battery Saving 1 1 0 Un_DET_out The result of No Signal Detection 1 1 1 PLL_LD The result of PLL lock detection D3 Set to 0 surely D2 D0 MONI2_SEL2 0 DET_TMONI2 Pin Output D2 MONI2_SEL2 D1 MONI2_SEL1 D0 MONI2_SEL0 Signal Name Description 0 0 0 Low level output 0 0 1 DET_out The result of ...

Page 67: ...0 1 1 DRSSI_out RSSI output voltage After the digital to analog conversion 1 0 0 Noise _out Noise detection output voltage 1 0 1 Peak_out Peak hold voltage of Peak Hold Circuit 1 1 0 Low level output 1 1 1 Low level output D3 Set to 0 surely D2 D0 MONI4_SEL2 0 DET_TMONI4 Pin Output When to select User Test h 10 D3 USER_TEST 1 and or MODE1 pin H these settings are valid D2 MONI4_SEL2 D1 MONI4_SEL1 ...

Page 68: ...e_Time4 Pre_Time3 Pre_Time2 Pre_Time1 Pre_Time0 Initial 1 0 0 1 1 1 1 0 Type R W R W R W R W R W R W R W R W h 18 D7 h 17 D7 D0 Pre_Time8 0 Preamble Signal Cycle When to set Preamble detection h 0F D6 Preamble_en 1 this setting is valid Setting Range h 18 D7 h 17 D7 D0 0 511 b 000000000 b 111111111 Initial Value 158 b 010011110 See section 6 5 6 about the Function of Preamble detection Notice The ...

Page 69: ...tting Table 6 72 Register h 19 D7 D6 D5 D4 D3 D2 D1 D0 Name Ndet_Th5 Ndet_Th4 Ndet_Th3 Ndet_Th2 Ndet_Th1 Ndet_Th0 Add_Hdet_ en Initial 0 0 0 0 0 0 0 0 Type R W R W R W R W R W R W R W R W D7 D2 Ndet_Th5 0 Noise Detector Threshold Level of Detection When to set FSK Demodulation h 0A D4 FSK_ASK 0 and Noise Detection h 0F D5 Ndet_en 1 this setting is valid Setting Range D7 D2 0 63 b 000000 b 111111 I...

Page 70: ...det 0 0 1 0 338ms 0 1 2 0 675ms 1 0 4 1 35 ms 1 1 8 2 70ms tdet Detection Interval fosc Reference Clock Frequency 30 32MHz n Coefficient determined by the setting of D7 D6 Ntime1 0 tdet n 1 fosc 256 40 sec Notice This tdet value in above table is derived from 30 32MHz Reference Clock Frequency To be valid the setting of this register setting finish writing the value to this register before the int...

Page 71: ...Judgment Detection Interval Signal Detection 0 0 0 3 Period 0 0 1 6 Bit 0 1 0 4 Period 0 1 1 8 Bit 1 0 0 5 Period Initial 1 0 1 10 Bit 1 1 0 6 Period 1 1 1 12bit No Signal Detection X X 0 3 Period Initial X X 1 4 bit X Don t care D1 Auto_Hdet_Off High Frequency Detector AutoOff When to set High Frequency Detection h 0F D4 Hdet_en 1 this setting is valid 0 Disable 1 Enable D0 NIR_H0 When to use NIR...

Page 72: ...ef2 0 Data Comparator reference Level Set the tracking time constant τ under the following conditions 1 No use of Data Comparator Quick Charge 1 2 2 Certain time has spent after starting Data Comparator Quick Charge 1 3 An absolute value of the difference between vref and vi Data comparator input voltage will be less than the threshold level set by register h 11 D7 D0 Charge2_Th7 0 tracking time c...

Page 73: ...6 5 7 about Peak Hold circuit Notice The cutoff frequency of Bit Rate Filter is derived from 30 32MHz Reference Clock Frequency D4 D3 Peak_Charge1 0 Limiter Peak Hold Voltage Charge Coefficient When to set ASK Demodulation h 0A D4 FSK_ASK 1 and Data Comparator Quick Charge 2 h 10 D6 Charge2_en 1 this setting is valid Set the charging time constant peak tracking of Peak Hold circuit Charge time con...

Page 74: ...00 b 11111111 Initial Value 0 b 00000000 Maximum 275 6ms b 00000000 Minimum 0ms b 00000001 The Maximum Minimum value of timer periods depend on 30 32MHz Reference Clock Frequency Way of setting n Setting value of register D7 D0 Ontime7 0 Setting value of timer period toff 215 fosc n 1 except n 0 Setting value of timer period toff 215 fosc 255 n 0 fosc Reference Clock Frequency 30 32MHz Notice To b...

Page 75: ...ef_diff2 Ref_diff1 Ref_diff0 Type R R R R R R R R D7 D0 Ref_diff7 0 Data Comparator Reference Level Drift Monitor 1 The output is 8 bit reference level drift of Data Comparator circuit It is available to monitor for the adjustment for the register setting of that circuit The output of 1 LSB will be equivalent to the drift of 1 1 53 kHz The output this register is the value b 11111111 when the drif...

Page 76: ...tal RSSI level When Digital RSSI circuit is disabled the output of this register is the value b 00000000 6 10 27 h 23 Noise Signal Level Monitor Table 6 82 Register h 23 D7 D6 D5 D4 D3 D2 D1 D0 Name DNDET7 DNDET6 DNDET5 DNDET4 DNDET3 DNDET2 DNDET1 DNDET0 Type R R R R R R R R D7 D0 DNDET7 0 Noise Detection Level Monitor The output is 8 bit Noise Detection level When Noise Detection circuit is disab...

Page 77: ...in voltage 3 RX_SW TX_SW Min 0 2 Max A_VDD_5V 0 2 or 6 0 Whichever is lower V Signal pin voltage RF_OUT PA_OUT Min 0 2 Max 3 6 V Maximum input power RF_IN Max 10 dBm Power dissipation PD Max 1 0 W Storage temperature range Tstg Min 55 Max 125 C The absolute maximum ratings of a semiconductor device are a set of specified parameter values which must not be exceeded during operation even for an inst...

Page 78: ... there are fluctuations in the electrical characteristics of a device 9 Electrical Data Unless otherwise specified Ta 25 C VDD 5 0V For 5V use fin RF 314 94MHz fin X_IN 30 32MHz Vin X_IN 1 5Vp p deviation 40kHz fmod 600Hz FSK modulation ENB High f IF 230kHz Wide band Set register h 0A D7 1 Set other registers initial Table 9 1 General Characteristics Characteristics Symbol Test Circuit Test Condit...

Page 79: ...tage input IIL2 5 μA Input high voltage 2 VIH2 A_VDD_5V 0 8 A_VDD_5V A_VDD_5V 0 2 V Leakage current 2 High voltage input IIH2 5 μA Output resistance ROH1 DATA_IO DET_TMONI1 DET_TMONI2 Low Drive 7 5 10 12 5 kΩ Output low voltage 1 VOL1 High Drive IOL 0 5mA 0 4 V Output high voltage 1 VOH1 IOH 0 5mA 4 6 V Output low voltage 2 VOL2 MISO Low Drive IOL 0 5mA 0 4 V Output high voltage 2 VOH2 IOH 0 5mA 4...

Page 80: ... 80 V RSSI output voltage 2 VRSSI2 11 5 VIN MIX 60dBm Unmodulated 0 85 1 25 1 60 V RSSI output voltage 3 VRSSI3 11 5 VIN MIX 30dBm Unmodulated 1 85 2 35 2 80 V RSSI output resistance RRSSI 11 3 37 5 50 62 5 kΩ Duty ratio DRfm 11 5 VIN MIX 60dBm DATA_IO pin output Data pattern 010101 45 50 55 Unless otherwise specified Ta 25 C VDD 5 0V For 5V use fin RF 314 94MHz fin X_IN 30 32MHz Vin X_IN 1 5Vp p ...

Page 81: ...117 dBm Receiver sensitivity 12dB SINAD2 12dB SINAD2 314 94 433 92MHz IF 230kHz Wide band FSK Deviation 40kHz 116 dBm Receiver sensitivity 12dB SINAD3 12dB SINAD3 915MHz IF 280kHz Middle band FSK Deviation 40kHz except for the harmonics of reference clock 116 dBm Receiver sensitivity 12dB SINAD4 12dB SINAD4 915MHz IF 230kHz Wide band FSK Deviation 40kHz except for the harmonics of reference clock ...

Page 82: ...smitting 3 IDD TX 3 Register h 13 D3 D2 01 8 8 mA Current consumption RF transmitting 4 IDD TX 4 Register h 13 D3 D2 00 Minimum level 7 3 mA RF transmitting power level 315MHz 2 PTX 315 2 Register h 13 D3 D2 10 8 dBm RF transmitting power level 315MHz 3 PTX 315 3 Register h 13 D3 D2 01 4 7 dBm RF transmitting power level 315MHz 4 PTX 315 4 Register h 13 D3 D2 00 Minimum level 0 dBm Table 10 4 Refe...

Page 83: ... by SW1 and SW2 SW3 and SW4 allow selecting the crystal oscillator and external signal Fig 11 1 Typical Test Circuit 19 20 21 22 24 25 26 27 23 9 8 7 6 4 3 2 5 36 35 34 33 32 31 30 29 28 16 17 18 13 14 15 10 11 12 TC32306FTG 0 1µF 100pF 100pF 100pF 0 1µF 7pF 7pF 30 32MHz 0 1µF 50Ω Line 0 1µF 0 1µF 0 01µF 330pF 1000pF 1000pF 0 1µF 1000pF 1000pF DET_TMONI2 DET_TMONI3 IO_GND DATA_IO DET_TMONI1 COM_VD...

Page 84: ... of RF Transmitting without PA operation set the register h13 D1 PA_en 0 Also in the measurement of RF Transmitting set the output pin via a 50Ω termination as illustrated In the measurement of Battery Saving Status set 3 pin to low level Fig 11 2 Test Circuit Current Consumption Test Characteristics RRSSI It will be measured at no voltage supply to TC32306FTG and applied lower voltage not to work...

Page 85: ...ing Test Characteristics PTX 315 1 In ASK measure by connecting the signal source to 35 pin In FSK measure by setting 35 pin to low level Set to unmodulated by register Fig 11 6 Test Circuit RF Transmitting 35 16 17 18 12 50 Line Signal Source Measuring Iinstrument TC32306FTG 11 12 50 Line 9 50 Line Signal Source Measuring Iinstrument TC32306FTG 6 35 Signal Source Measuring Instrument a Measuring ...

Page 86: ...VDD V Current consumption I DD mA Current consumption I DD mA FSK Current Consumption vs Power Supply Voltage Characteristics 314 94MHz FSK Current Consumption vs Power Supply Voltage Characteristics 433 92MHz Power supply voltage VDD V Power supply voltage VDD V Current consumption I DD mA Current consumption I DD mA FSK Current Consumption vs Power Supply Voltage Characteristics 915MHz FSK Curre...

Page 87: ... MIX IN dBm RSSI output voltage V RSSI V RSSI output voltage V RSSI V 0 2 4 6 8 10 12 14 0 1 2 3 4 5 VDD 5V use f RF in 314 94MHz ASK mode Meas point VDD at multi meter 115 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 130 110 90 70 50 30 10 10 915MHz RF IN 314 94MHz RF IN 433 92MHz RF IN 314 94MHz MIX IN 433 92MHz MIX IN 915MHz MIX IN VDD 3 0V 3V use IFBW 320kHz Meas point RSSI_OUT at multi meter 0 0 5 1 1 5 2...

Page 88: ...detection IF RF IN kHz IF RF IN kHz S curve output voltage V S curve output voltage V 12dB SINAD Sensitivity Characteristics ASK 12dB SINAD Sensitivity Characteristics FSK IF RF IN kHz IF RF IN kHz 12dB SINAD sensitivity dBm 12dB SINAD sensitivity dBm S N AMR Characteristics RF input Un modulated Signal Interference Characteristics FSK RF IN input level P RF IN dBm RF IN interference frequency IF ...

Page 89: ...ltage level Output voltage V Voltage level Output voltage V Voltage level 0 4 0 2 0 0 0 2 0 4 0 6 0 8 1 0 1 2 1 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 ENB DATA_IO BRF_out Data_compREF VDD 5 0V 5V use f RF in 314 94MHz fmod 600Hz ASK 100 Charge2 enable Meas point ENB DET_TMONI3 DET_TMONI4 DATA_IO at oscilloscope H L H L 0 4 0 2 0 0 0 2 0 4 0 6 0 8 1 0 1 2 0 2 0 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 1 6 1 8 L H ...

Page 90: ...cteristics PA Output Level Characteristics vs TX Current Consumption Power supply voltage VDD V Current consumption IDD mA Current consumption I DD mA PA output level dBm PA output level dBm 0 2 4 6 8 10 12 14 16 0 1 2 3 4 5 VDD 5V use FSK mode PA maximum output Meas point VDD at multi meter 314 94MHz 433 92MHz 915MHz 0 2 4 6 8 10 12 14 0 1 2 3 4 5 VDD 5V use FSK mode f RF out 314 94MHz PA maximum...

Page 91: ... 2 4 6 8 10 12 280 290 300 310 320 330 340 VDD 3 0V 3V use FSK mode 315MHz operation PA maximum output Meas point PA_OUT at spectrum analyzer PA Output Level Frequency Characteristics RF output frequency MHz PA output level dBm ...

Page 92: ...MIX FSK ASK LNA Limiter RX TX 100k 0 1µF 0 1µF 1000pF 1000pF 0 1µF 0 1µF 0 1µF 0 1µF VDD PC C3 C4 C5 L1 L2 L3 L4 C10 C11 30 32MHz 0 1uF X1 27pF 6pF 56nH 51nH 3pF 330pF 100nH 36nH C6 12pF C1 C2 27pF RX_IN TX_OUT 0 01µF 1SS387 Power ON RESET SW2 SW1 TC32306FTG 19 20 21 22 24 25 26 27 23 9 8 7 6 4 3 2 5 35 34 33 32 31 30 29 28 16 17 18 13 14 15 10 11 12 36 1 C7 330pF 100k 1k R1 1k 100 100k 100k DET_ ...

Page 93: ... following Murata Manufacturing Company Ltd i TZY2Z060A001 6pF ii TZY2Z030A001 3pF iii TZY2Z010A001 1pF The inductance L1 L4 LQW18 series Murata Manufacturing Company Ltd X1 FCX 04 30 320MHZ J90842 RIVER ELETEC CORPORATION C10 9pF C11 9pF Or NX3225SC EXS00A CS03981 30 320MHz NIHON DEMPA KOGYO CO LTD C10 9pF C11 9pF Or CX3225SA30320B0GPQCC KYOCERA Crystal Device Corporation C10 10pF C11 9pF Table 1...

Page 94: ...V308 Toshiba Corporation About resistors capacitors and coils values in the circuit consider referring to the evaluation circuit of section 13 1 IF Filter Detector LPF RSSI ADC LPF BRF Data COMP VCO Divider PLL XOSC Monitor SPI Reference clock IF AMP PA MIX FSK ASK LNA Limiter RX TX 0 1µF 0 1µF SAW Filter 1000pF 1000pF 0 1µF 0 1µF 0 1µF 0 1µF VDD SW1 1SV308 1SV308 MCU C3 C5 L1 L2 L3 L4 C10 C11 30 ...

Page 95: ... signal About resistors capacitors and coils values in the circuit consider referring to the evaluation circuit of section 13 1 IF Filter Detector LPF RSSI ADC LPF BRF Data COMP VCO Divider PLL XOSC Monitor SPI Reference clock IF AMP PA MIX FSK ASK LNA Limiter RX TX 0 1µF 0 1µF 1000pF 1000pF 0 1µF 0 1µF 0 1µF 0 1µF VDD MCU C5 L3 L4 C10 C11 30 32MHz 0 1µF X1 R1 C6 TC32306FTG 19 20 21 22 24 25 26 27...

Page 96: ... About EEPROM pin termination see that manual for example SPI Serial EEPROM S 25A010A 020A 040A series Seiko Instruments Inc About resistors capacitors and coils values in the circuit consider referring to the evaluation circuit of section 13 1 IF Filter Detector LPF RSSI ADC LPF BRF Data COMP VCO Divider PLL XOSC Monitor SPI Reference clock IF AMP PA MIX FSK ASK LNA Limiter RX TX 0 1µF 0 1µF 1000...

Page 97: ... signal In EEPROM Mode this IC doesn t prepare antenna switch control About EEPROM pin termination see that manual About resistors capacitors and coils values in the circuit consider referring to the evaluation circuit of section 13 1 IF Filter Detector LPF RSSI ADC LPF BRF Data COMP VCO Divider PLL XOSC Monitor SPI Reference clock IF AMP PA MIX FSK ASK LNA Limiter RX TX 0 1µF 0 1µF 1000pF 1000pF ...

Page 98: ...g Top View Lot Code 1 The year of manufacture 1 last figure of the year 2 The week of manufacture 01 as first week of the year from 1 to 52 or 53 3 Toshiba factory management code 4 Assembly code 1 2 3 4 Mark of 1Pin Product name 32306 ...

Page 99: ...TC32306FTG 2015 10 01 99 15 Package Dimensions Weight 0 08g Typ Unit mm QFN36 P 0606 0 50 ...

Page 100: ...OCAL OSCILLATOR 19 6 4 1 Local Oscillation Abstracts 19 6 4 2 Reference Clock 19 6 4 3 Local Oscillation 19 6 5 RF RECEIVER 20 6 5 1 RF Receiving Abstract 20 6 5 2 Receiving Frequency Band 21 6 5 3 Receiver Gain 21 6 5 4 IF Frequency 22 6 5 5 Demodulation 22 6 5 6 FSK Demodulation 22 6 5 7 ASK Demodulation 26 6 5 8 Bit Rate Filter 27 6 5 9 Data Comparator 27 6 6 RF TRANSMITTER 29 6 6 1 RF Transmit...

Page 101: ...amble Detector Setting 1 68 6 10 16 h 18 Preamble Detector Settings 2 68 6 10 17 h 19 Noise Detector Threshold Setting 69 6 10 18 h 1A Signal Detector Settings 70 6 10 19 h 1B Data Comparator Settings 71 6 10 20 h 1C Peak Hold Settings 73 6 10 21 h 1D AutoOff Type B Setting 74 6 10 22 h 1E Signal Detect and Lock Detect Monitors 74 6 10 23 h 1F Peak Hold Level Monitor 75 6 10 24 h 20 Data Comparato...

Page 102: ...ships and other transportation traffic signaling equipment equipment used to control combustions or explosions safety devices elevators and escalators devices related to electric power and equipment used in finance related fields IF YOU USE PRODUCT FOR UNINTENDED USE TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT For details please contact your TOSHIBA sales representative Do not disassemble analyze rev...

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Summary of Contents for TC32306FTG

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Toshiba TC32306FTG, Manual, Page: 7 / 102

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