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SNAS724 – FEBRUARY 2018
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The LOL flags can be observed through status pins for all APLLs and DPLLs, as well as through the
corresponding interrupt register bits.
9.3.7.5 Tuning Word History
Each REF-DPLL domain has a tuning word history monitor block that determines the initial output frequency
accuracy upon entry into holdover. The tuning word can be updated from one of three sources depending on the
DPLL operating mode:
a. Locked Mode: From the output of the digital loop filter when locked
b. Holdover Mode: From the final output of the history monitor
c. Free Run Mode: From the free-run tuning word register (user defined)
When the history monitor is enabled and the DPLL is locked, it effectively averages the reference input frequency
by accumulating history from the digital loop filter output during a programmable averaging time (Tavg). Once the
input becomes invalid, the final tuning word value is stored to determine the initial holdover frequency accuracy.
Generally, a longer the Tavg time will produce a more accurate initial holdover frequency. The stability of 0-ppm
reference clock (XO or TCXO input) determines the long-term stability and accuracy of the holdover output
frequency.
There is also a separate programmable delay timer (Tign) that can be set to ignore the history data that is
corrupted just prior to entry into holdover. The history data could be corrupted if a tuning word update occurs
while the input clock is failing and before it is detected by the input monitors. Both Tavg and Tign times are
programmable through HISTCNT and HISTDLY bits, respectively, and are related to the REF-TDC rate.
The tuning word history is initial cleared after a device hard reset or soft reset. The history monitor begins to
accumulate history once the DPLL locks to a new reference. The previous history will be cleared when a
switchover to a new reference occurs assuming the history persistence bit (HIST_HOLD) is not set. The history
can be manually cleared by asserting the history soft reset bit (HIST_SW_RST). If the history persistence bit is
set, the history monitor will not clear the previous history value during reference switchover, holdover exit, or
history soft reset. Whenever the tuning word is cleared, the history monitor waits for the first Tavg timer to expire
before storing the first tuning word value.
If the Tavg period is set very long (minutes or hours) to a more precise historical average frequency, it is possible
for a switchover or holdover event to occur before the first tuning word is stored and available for use. To
overcome this, there is an intermediate history update option (HIST_INTMD). If the history is reset, then the
intermediate average can be updated at intervals of Tavg/2
K
, where K = HIST_INTMD to 0,
during the first Tavg
period only
. If HIST_INTMD = 0, there is no intermediate updates and the first average is stored after the first
Tavg period. However, if HIST_INTMD = 4, then four intermediate averages are taken at Tavg/16, Tavg/8,
Tavg/4, and Tavg/2, as well as at Tavg. After the first Tavg period, all subsequent history updates occur at the
Tavg period.
When the history monitor is disabled, the user-programmable, free-run tuning word value (TUNING_FREE_RUN)
determines the initial holdover output frequency accuracy.
9.3.7.6 Status Outputs
STATUS[1:0] and GPIO[6:5] pins can be used to output various internal status signals or interrupt flag for device
diagnostic or debug purposes. The status signal, output driver type, and output polarity settings are configurable
by registers.
The following lists the available status outputs (active high):
•
XO Input Loss of Signal (LOS)
•
TCXO Input Loss of Signal (LOS)
•
PLLy Lock Detected (LOLb)
•
PLLy VCO Calibration Active
•
PLLy N Divider, div-by-2
•
EEPROM Active
•
Interrupt (INTR)
•
PLLy VCO div-by-96
•
REFx monitor divider output, div-by-2
Summary of Contents for LMK05028
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