ADV
ANCEINFORMA
TION
14
SNAS724 – FEBRUARY 2018
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Copyright © 2018, Texas Instruments Incorporated
SPI Timing Requirements (SDA, SCL, GPIO1/SCS, GPIO2/SDO) (continued)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, T
A
= –40ºC to 85ºC
PARAMETER
MIN
NOM
MAX
UNIT
t
6
SCL to SDO valid read-back data
10
TBD
ns
t
7
SCS pulse width
20
ns
t
8
SCS to CLK hold time
10
ns
(1)
Parameter is specified by characterization and is not tested in production.
7.21 Other Characteristics
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, T
A
= –40ºC to 85ºC, OUTx = 156.25 MHz, Differential
output pair AC-coupled to 100-
Ω
differential load, HCSL output pair terminated with 50
Ω
to GND, LVCMOS output terminated
with 50
Ω
to VDDO / 2.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
t
PHO,CMO
S
IN-to-OUT Phase Offset,
LVCMOS outputs
(1)
Zero delay enabled
TBD
ns
t
PHO,DIFF
IN-to-OUT Phase Offset, DIFF
outputs
(1)
Zero delay enabled
TBD
ns
PSNR
Spur level induced by power
supply noise (V
N
= 50 mVpp)
VDDO_x = 2.5 V or 3.3 V, AC-Diff or
HCSL output
–70
dBc
VDDO_x = 2.5 V, LVCMOS output
–55
dBc
PSNR
Spur level induced by power
supply noise (V
N
= 25 mVpp)
VDDO_x = 1.8 V, AC-Diff or HCSL output
–70
dBc
VDDO_x = 1.8 V, LVCMOS output
–45
dBc
SPUR
Spur level due to isolation/cross
coupling (adjacent outputs)
OUTx = 156.25 MHz, OUTy = 155.52
MHz, AC-Diff or HCSL (same output type
for both channels)
–75
dBc
(1)
Parameter is specified by characterization and is not tested in production.
(2)
Actual loop bandwidth may be lower. Applies to REF-DPLL and TCXO-DPLL. The valid loop bandwidth range may be constrained by
the DPLL loop mode and REF and/or TCXO input frequencies used in a given configuration.
(3)
First PLL domain to start-up is selected by PLLSTRTMODE bit. Assumes XO input clock is stable before rising edge of PDN, PLL/VCO
wait timers set to 3 ms/0.4 ms, and output channels auto-muted during APLL lock only.
7.22 PLL Clock Output Performance Characteristics
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, T
A
= –40ºC to 85ºC, OUTx = 156.25 MHz, Differential
output pair AC-coupled to 100-
Ω
differential load, HCSL output pair terminated with 50
Ω
to GND, LVCMOS output terminated
with 50
Ω
to VDDO / 2.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
RJ
RMS Phase Jitter
(1)
(12
kHz – 20 MHz)
OUT = 156.25 MHz AC-Diff or HCSL, XO =
48.0048 MHz
150
225
fs RMS
PN-TDC
Output Close-in Phase
Noise (f
OFFSET
= 100 Hz)
OUT = 122.88 MHz AC-Diff or HCSL, IN = 10
MHz, XO = 48.0048 MHz, LBW = 100 Hz
–102
dBc/Hz
LBW
DPLL Loop Bandwidth
Range
(1) (2)
Programmed bandwidth setting
0.01 to
4000
Hz
JPK
Jitter Peaking
(1)
IN = 25 MHz, OUT = 25 MHz, DPLL BW = TBD
Hz
0.1
dB
JTOL
Jitter tolerance
(1)
Jitter Modulation = 10 Hz, 10.3125 Gbps
2488
UI p-p
PHTR
Maximum phase transient
during Hitless Switch
(1)
Valid for a single switchover event between two
clock inputs at the same frequency
±100
ps
f
ERROR
Maximum additive
frequency error
(1)
Valid for a single switchover event between two
clock inputs at the same frequency
100
ppb
t
START-XO
Initial Clock Start-up Time
(3)
From rising edge of PDN to free-running output
clocks from first PLL domain
20
ms
STD
Standards Compliance
G.813 Opt. 1
G.8262 Opt. 1 and 2
G.709
GR-253-CORE
GR-1244 CORE
Summary of Contents for LMK05028
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