![background image](http://html.mh-extra.com/html/texas-instruments/lmk05028/lmk05028_advance-information_1097089042.webp)
ADV
ANCEINFORMA
TION
SCL
SCS
SDO
t
4
t
5
t
2
t
3
t
7
t
6
t
1
§
§
§
SDI
§
§
t
8
W/R
D0
D1
D7
D1
D0
A14
'21¶7 &$5(
'21¶7 &$5(
§
²
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
14
A
13
A
12
A
11
W
/R
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Register Address (15 bits)
Data Payload (8 bits)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22
23
24
Message Field Definition
Bit Definition
Order of Transmission
First Out
42
SNAS724 – FEBRUARY 2018
Product Folder Links:
Copyright © 2018, Texas Instruments Incorporated
Programming (continued)
9.5.3 SPI Serial Interface
When started in SPI mode (HW_SW_CTRL = float), the LMK05028 uses a 4-wire SPI interface with SDI, SCL,
SDO, and SCS signals. The host must present data to the device MSB first. A message includes a transfer
direction bit (W/R), a 15-bit address field (A14 to A0), and a 8-bit data field (D7 to D0) as shown in
.
The W/R bit is 0 for a SPI write and 1 for a SPI read.
Figure 40. SPI Message Format
The SPI timing diagram is shown in
.
Figure 41. SPI Timing Parameters
9.5.4 EEPROM Programming Flow
After the configuration registers are programmed, the EEPROM can be programmed by the register writes in two
steps: Write SRAM and Program EEPROM.
9.5.4.1 Write SRAM
The SRAM array is volatile
shadow
memory mapped to a subset of the active configuration registers that
determine the device operation at POR or initialization. After the active registers have been programmed, they
can be committed to the SRAM through the following sequence:
1. Write a 0 to REGCOMMIT_PG bits.
2. Write a 1 to REGCOMMIT bit (self-clearing). This transfers the active register data to the SRAM internally.
If the SRAM/EEPROM map data is already known, the SRAM can also be written directly
without modifying the
active configuration registers
through the following sequence:
1. Write the 4 upper bits of the SRAM address to MEMADR[12:8] bits and write 8 lower bits of the SRAM
address to MEMADR[7:0] bits.
2. Write the desired SRAM data byte to RAMDAT bits in the same I2C or SPI transaction and this data byte will
be written at the SRAM address specified in the previous step. Any additional access that is part of the same
transaction will cause the SRAM address to be auto-incremented and a subsequent write will take place to
the next SRAM address. Access to SRAM will terminate at the end of current I2C or SPI transaction.
Summary of Contents for LMK05028
Page 57: ......