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ANCEINFORMA
TION
50
SNAS724 – FEBRUARY 2018
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Configure the DPLL input selection modes and input priorities through the registers.
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Output clock assignment guidelines to minimize crosstalk and spurs:
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OUT[4:7] bank requires at least one clock from the PLL1 domain. OUT[4:7] bank is preferred for PLL1
clocks.
–
OUT[0:3] bank requires at least one clock from the PLL2 domain if enabled. OUT[0:3] bank is
preferred for PLL2 clocks.
–
Group identical output frequencies (or harmonic frequencies) on adjacent channels. Use the output
pairs with a single divider (OUT2/3 or OUT4/5) if possible to minimize power.
–
Separate clock outputs when the difference of the two frequencies, |F
OUTx
- F
OUTy
|, falls within the jitter
integration bandwidth (12 kHz to 20 MHz, for example). The two outputs should be separated by at
least 4 static pins (power or logic) to minimize potential coupling, or consider placing them on separate
output banks (which are on opposite sides of the chip).
–
Avoid or isolate any LVCMOS output (strong aggressor) from other jitter-sensitive differential output
clocks. If a LVCMOS output is required, use dual complementary LVCMOS mode (+/- or -/+) with the
unused LVCMOS output left floating with no trace. Furthermore, the output slew rate could also be
slowed to Normal mode (CHx_SLEW_RATE bit) to reduce the coupling strength of an LVCMOS
output.
–
If not all outputs pairs are used in the application, consider connecting OUT0 or OUT1 to a pair of RF
coaxial test structures for testing purposes (such as SMA, SMP). OUT0 and OUT1 are capable of
selecting a buffered copy of the XO clock or the Ref Bypass clock (either DPLL reference or TCXO
input) as well as any PLL post-divider clock.
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Clock outputs: Follow the single-ended or differential clock output interface examples in
–
Configure each clock output buffer mode through registers to match the receiver interface
requirements.
–
Differential outputs should be AC-coupled and terminated or biased at the receiver inputs.
–
HCSL outputs should have 50-
Ω
termination to GND (at source or load side) unless the internal
source termination is enabled by registers.
–
LVCMOS outputs have internal source termination to drive 50-
Ω
traces directly. LVCMOS V
OH
level is
determined by VDDO voltage (1.8 V and 2.5 V).
–
Configure the DPLL loop mode.
–
3-loop mode supports standards-compliant synchronization using a low-cost holdover TCXO/OCXO,
very low loop bandwidths (
≤
10 Hz), or both. 3-loop mode also supports 1-PPS input synchronization.
–
2-loop mode with REF-DPLL supports higher loop bandwidth (>10 Hz) and relaxed holdover stability
without a TCXO/OCXO.
–
2-loop mode with TCXO-DPLL locks to a TCXO/OCXO input and typically used with DCO mode for
external clock steering (such as IEEE 1588 PTP).
–
Configure the REF-DPLL loop bandwidth.
–
The optimal bandwidth depends on the relative phase noise between the reference input and the XO
(or the TCXO for 3-loop mode).
–
For 3-loop mode, the bandwidth is typically 10 mHz to 10 Hz to attenuate wander and support low
wander generation because of the TCXO/OCXO.
–
For 2-loop mode, the bandwidth is typically 10 Hz or higher. Target a bandwidth below 300 Hz if the
PLL VCO frequency is an integer multiple of the reference input frequency.
–
Below the loop bandwidth, the reference noise is added to the REF-TDC noise floor (and the XO
noise in 2-loop mode). Above the loop bandwidth, the reference noise will be attenuated at 20
dB/decade.
–
Configure the TCXO-DPLL loop bandwidth.
–
The optimal bandwidth depends on the relative phase noise between the TCXO/OCXO and the XO.
–
For 3-loop mode, the bandwidth should be at least 200x higher than the REF-DPLL bandwidth for loop
stability.
–
For 2-loop mode with TCXO-DPLL, target a bandwidth below 300 Hz if the PLL VCO frequency is an
integer multiple of the TCXO/OCXO frequency.
–
Below the loop bandwidth, the TCXO/OCXO noise is added to the TCXO-TDC noise floor. Above the
loop bandwidth, the OCXO/TCXO noise will be attenuated at 20 dB/decade.
Summary of Contents for LMK05028
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