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ADV
ANCEINFORMA
TION
6
SNAS724 – FEBRUARY 2018
Product Folder Links:
Copyright © 2018, Texas Instruments Incorporated
Pin Functions (continued)
PIN
TYPE
(1)
DESCRIPTION
NAME
NO.
(2)
Internal resistors: PDN pin has 200-k
Ω
pullup to VDD. Each HW_SW_CTRL, GPIO, and STATUS pin has a 150-k
Ω
bias to V
IM
(~0.9 V)
when PDN = 0 or 400-k
Ω
pulldown when PDN = 1. Each INSEL pin has a 85-k
Ω
pullup to 1.8 V when PDN = 0 or 400-k
Ω
pulldown
when PDN = 1.
(3)
Unless otherwise noted: Logic inputs are 2-level, 1.8-V compatible inputs. Logic outputs are 3.3-V LVCMOS levels.
OUT4_P
51
O
Clock Outputs 4 to 7 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or
1.8/2.5-V LVCMOS clocks (one or two per pair). Unused differential outputs should be terminated if
active or left floating if disabled through registers.
The OUT[4:7] bank requires at least one clock from PLL1 domain. This bank is preferred for PLL1
clocks to minimize output crosstalk.
OUT4_N
52
O
OUT5_P
54
O
OUT5_N
53
O
OUT6_P
57
O
OUT6_N
58
O
OUT7_P
62
O
OUT7_N
61
O
LOGIC CONTROL / STATUS
(2) (3)
HW_SW_CTRL
64
I
Device Start-Up Mode Select
(3-level, 1.8-V compatible).
This input selects the device start-up mode that determines the memory page used to initialize the
registers, serial interface, and logic pin functions. The input level is sampled only at device power-
on reset (POR).
See
for start-up mode descriptions and logic pin functions.
PDN
46
I
Device Power-Down
(active low).
When PDN is pulled low, the device is in hard reset and all blocks including the serial interface are
powered-down. When PDN is pulled high, the device is started according to device mode selected
by HW_SW_CTRL and begins normal operation with all internal circuits reset to their initial state.
SDA/SDI
35
I/O
I2C Serial Data I/O (SDA) or SPI Serial Data Input (SDI).
See
.
The default 7-bit I2C address is 11000xxb, where the MSB bits (11000b) are initialized from on-chip
EEPROM and the LSB bits (xxb) are determined by the logic input pins. When HW_SW_CTRL is 0,
the LSBs are determined by the GPIO[2:1] input levels during POR. When HW_SW_CTRL is 1, the
LSBs are fixed to 00b.
SCL/SCK
36
I
I2C Serial Clock Input (SCL) or SPI Serial Clock Input (SCK).
See
GPIO0/SYNCN
45
I
Multifunction Inputs or Outputs.
See
.
GPIO1/SCS
24
I
GPIO2/SDO
60
I/O
GPIO3/FINC1
40
I
GPIO4/FDEC1
41
I
GPIO5/FINC2
12
I/O
GPIO6/FDEC2
13
I/O
STATUS1
56
I/O
Status Outputs [1:0].
Each output has programmable status signal selection, driver type (3.3-V LVCMOS or open-drain),
and status polarity. Open-drain requires an external pullup resistor. Leave pin floating if unused.
STATUS0
55
I/O
INSEL0_1
17
I
Manual Reference Input Selection for DPLL1.
INSEL0_[1:0] = 00b (IN0), 01b (IN1), 10b (IN2), or 11b (IN3). Leave pin floating if unused.
INSEL0_0
20
I
INSEL1_1
29
I
Manual Reference Input Selection for DPLL2.
INSEL1_[1:0] = 00b (IN0), 01b (IN1), 10b (IN2), or 11b (IN3). Leave pin floating if unused.
INSEL1_0
28
I
Summary of Contents for LMK05028
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