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ANCEINFORMA
TION
31
SNAS724 – FEBRUARY 2018
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•
DEN
APLL
: APLL feedback N divider denominator value (40 bits, 1 to 2
40
)
(1)
relates to the TCXO-DPLL.
F
VCO
= (F
TCXO
× D
TCXO
/ MDIV) × P1 × PR
TCXO-DPLL
× (INT
TCXO-DPLL
+ NUM
TCXO-DPLL
/ DEN
TCXO-DPLL
)
where
•
F
VCO
: APLL/VCO frequency
•
F
TCXO
: TCXO/OCXO input frequency
•
D
TCXO
: TCXO input doubler, 1 = disabled and 2 = enabled
•
M: TCXO input divider (5 bits, 1 to 32)
•
P1 = PLL primary post-divider (4 to 9, 11, 13)
•
PR
TCXO-DPLL
: TCXO-DPLL feedback prescaler divider (2 to 17)
•
INT
TCXO-DPLL
: TCXO-DPLL feedback divider integer value (30 bits, 1 to 2
30
-1)
•
NUM
TCXO-DPLL
: TCXO-DPLL feedback divider numerator value (40 bits, 0 to 2
40
-1)
•
DEN
TCXO-DPLL
: TCXO-DPLL feedback divider denominator value (fixed, 2
40
)
(2)
relates to the REF-DPLL.
F
VCO
= (F
INx
/ Rx) × P1 × PR
REF-DPLL
× (INT
REF-DPLL
+ NUM
REF-DPLL
/ DEN
REF-DPLL
)
where
•
F
VCO
: APLL/VCO frequency
•
F
INx
: Reference input (0 to 3) or VCO loopback frequency (IN4 = VCO2, IN5 for VCO1)
•
Rx: Reference input divider (16 bits, 1 to 2
16
-1) (x = 0 to 5)
•
PR
REF-DPLL
: REF-DPLL feedback prescaler divider (2 to 17)
•
INT
REF-DPLL
: REF-DPLL feedback divider integer value (30 bits, 1 to 2
30
-1)
•
NUM
REF-DPLL
: TCXO-DPLL feedback divider numerator value (40 bits, 0 to 0 to 2
40
-1)
•
DEN
REF-DPLL
: REF-DPLL feedback divider denominator value (40 bits, 1 to 2
40
)
(3)
relates to any reference inputs assigned to a DPLL to ensure a constant REF-TDC rate for proper
input switchover.
F
REF-TDC
= F
IN0
/R0 = F
IN1
/R1 = F
IN2
/R2 = F
IN3
/R3
(4)
,
, and
relate to the output frequency according to the source selected by the
output channel mux (CH_x_MUX).
F
OUTx
= F
XO
or F
REF
when XO or Ref Bypass is selected (OUT0 or OUT1 only)
(5)
F
OUTx
= F
VCO
/ (Pn × DIVA
OUTx
) when PLL post-divider is selected
(6)
F
OUTx
= F
VCO
/ (Pn × DIVA
OUTx
× DIVB
OUTx
) when PLL post-divider is selected (OUT0 or OUT7 only)
where
•
F
REF
: TCXO, DPLL1 Ref, or DPLL2 Ref input frequency selected by REF_BYPASS_MUX
•
Pn: P1 or P2 post divider value for PLL1 or PLL2
•
DIVA
OUTx
: Output divider value (20 bits, 1 to 2
20
-1)
•
DIVB
OUTx
: Output divider MSB value (11 bits, 1 to 2
11
-1)
(7)
9.3.8.3 APLL XO Doubler
Each APLL has a frequency doubler on the XO input that can be enabled (default) to double the APLL PFD rate
for improved phase noise and jitter performance within the APLL loop bandwidth.
9.3.8.4 APLL Phase Frequency Detector (PFD)
The PFD frequency of each APLL can operate from 10 MHz to 200 MHz, but the APLL performance is optimized
for PFD frequencies at 96 MHz or higher.
9.3.8.5 APLL Charge Pump
Each PLL has programmable charge pump settings of 1.6 mA, 3.2 mA, 4.8 mA, or 6.4 mA.
Summary of Contents for LMK05028
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